State Transitions During Counter Operation - Fujitsu F2MC-16LX Hardware Manual

CHAPTER 16 16-BIT RELOAD TIMER

16.3.1 State Transitions During Counter Operation

This section describes the state transitions during counter operation.
I State transitions during counter operation
Reset
WAIT state
CNTE=1, WAIT=1
TIN pin: Valid for trigger input only
TOT pin: 16-bit reload register value output
16-bit timer register: Retains the value at stop.
(Software trigger)
External trigger from TIN
: State transition by hardware
: State transition by register access
: WAIT signal (internal signal)
WAIT
: Software trigger bit (TMCSR)
TRG
: Timer counter enable bit (TMCSR)
CNTE
: Timer interrupt request flag bit (TMCSR)
UF
: Reload operation enable bit (TMCSR)
RELD
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Figure 16.3-3 State transition during counter operation
STOP state
TIN pin: Input disabled
TOT pin: General-purpose input/output port
16-bit timer register: Retains the value at stop.
CNTE=0
CNTE=1
TRG=0
UF=1 &
RELD=0
Not specified until loading
(One-shot mode)
after reset
TRG=1
LOAD
Loads the 16-bit reload register value
into the 16-bit timer register
CNTE=0, WAIT=1
Not specified immediately
after reset
CNTE=1
TRG=1
RUN state
TIN pin: Functions as input pin of the 16-bit reload timer
TOT pin: Functions as output pin of the 16-bit reload timer
16-bit timer register: Count operation
UF=1 &
RELD=1
(Reload mode)
(Software trigger)
CNTE=1, WAIT=0
CNTE=0
CNTE=1, WAIT=0
TRG=1
Load end