Counter Operation State; Figure 15.4.7A Counter State Transitions - Fujitsu F2MC-16LX MB90580 Series Hardware Manual
16-bit microcontrollers
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Also See for F2MC-16LX MB90580 Series:
- Hardware manual (706 pages) ,
- Application note (13 pages) ,
- Operation manual (10 pages)
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15.4.7 Counter operation state
The counter state is determined by the CNTE bit in the control register and the internal WAIT signal. Avail-
able states are: CNTE = "0" and WAIT = "1" (STOP state), CNTE = "1" and WAIT = "1" (WAIT state for trig-
ger), and CNTE = "1" and WAIT = "0" (RUN state). Figure 15.4.7a shows the transitions between each
state.
Reset
CNTE='0'
WAIT
Counter: Stores the value when
counting stopped.
Undefined just after a reset until
loaded.
STOP
Counter: Stores the value when
counting stopped.
Undefined immediately after a reset.
CNTE='1'
TRG='0'
CNTE=1, WAIT=1
RELD
TRG='1'
LOAD
Load contents of the reload
register to the counter.
Figure 15.4.7a Counter State Transitions
CNTE=0, WAIT=1
CNTE='1'
TRG='1'
RUN
Counter: Running
·UF
TRG='1'
RELD·UF
CNTE=1, WAIT= 0
State transitions by hardware
State transitions by register access
CNTE='0'
CNTE=1, WAIT=0
Load complete
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