Register And Register Details; Clock Division Control Registers - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

11.3 Register and Register Details

11.3 Register and Register Details

11.3.1 Clock Division Control Registers

Clock Division Control Register 0, 1, 2, 3, 4
Address : 00002C
00002E
000034
000087
00008F
Read/write
Initial value
[bit 15] MD (Machine clock divide mode select):
This bit is used to control the operation of the communication prescaler.
The communication prescaler is disabled.
0
1 The communication prescaler is enabled.
[bits 11, 10, 9, and 8] DIV3 to DIV0 (Divide 3 to 0):
These bits are used to determine the machine clock division ratio.
DIV3 DIV2
1 1
1 1
1 1
1 1
1 0
1 0
1 0
1 0
Note: When the division ratio is changed, allow two cycles for the clock to stabilize before
starting communication.
Note: In actual application, please use the values other than '1111'.
120 Chapter 11: Communication Prescaler
H
15 14 13
H
H
— —
MD
H
H
(R/W) (–) (–)
(0) (–) (–)
DIV1 DIV0
1 1 Reserved
1 0
0 1
0 0
1 1
1 0
0 1
0 0
12 11 10
—
DIV3 DIV2
(–) (R/W) (R/W)
(–) (1) (1)
Division ratio
2
3
4
5
6
7
8
9 8
Bit number
CDCR0
DIV1 DIV0
CDCR1
CDCR2
CDCR3
CDCR4
(R/W) (R/W)
(1) (1)
[initial value]
[initial value]
MB90580 Series