Freescale Semiconductor e200z3 Reference Manual page 203

Table 4-13. Instruction Storage Interrupt Register Settings
Register
SRR0 Set to the effective address of the excepting instruction.
SRR1 Set to the contents of the MSR at the time of the interrupt
MSR UCLE 0
SPE 0
WE 0
CE —
EE 0
ESR [XTE, BO, MIF, VLEMI]. All other bits cleared.
MCSR Unchanged
DEAR Unchanged
Vector IVPR[32–47] || IVOR3[48–59] || 0b0000
4.6.5 External Input Interrupt (IVOR4)
An external input exception is signaled to the processor by the assertion of the external interrupt input
(p_extint_b), a level-sensitive signal expected to remain asserted until the e200z3 acknowledges the
external interrupt. If p_extint_b is negated early, recognition of the interrupt request is not guaranteed.
When the e200z3 detects the exception, if the exception is enabled by MSR[EE], the e200z3 takes an
external input interrupt.
An external input interrupt may be delayed by other higher priority exceptions or if MSR[EE] is cleared
when the exception occurs.
Table 4-14 lists register settings when an external input interrupt is taken.
Register
SRR0 Set to the effective address of the instruction the processor would attempt to execute next if no exception were
present.
SRR1 Set to the contents of the MSR at the time of the interrupt
MSR UCLE 0
SPE 0
WE 0
CE —
EE 0
ESR Unchanged
MCSR Unchanged
DEAR Unchanged
Vector IVPR[32–47] || IVOR4[48–59] || 0b0000
IVPR[32–47] || p_voffset[0:11] || 0b0000 (non-autovectored)
Freescale Semiconductor
Setting Description
PR 0
FP 0
ME —
FE0 0
Table 4-14. External Input Interrupt Register Settings
Setting Description
PR 0
FP 0
ME —
FE0 0
e200z3 Power Architecture Core Reference Manual, Rev. 2
Interrupts and Exceptions
DE —
FE1 0
IS 0
DS 0
RI —
DE —
FE1 0
IS 0
DS 0
RI —
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