Freescale Semiconductor e200z3 Reference Manual page 236

Memory Management Unit
5.6.2 TLB0 and TLB1 Configuration Registers
TLB0CFG and TLB1CFG provide configuration information for the MMU TLBs supplied with this
version of the e200z3 CPU core. See
5.6.3 Data Exception Address Register (DEAR)
DEAR, described in Section 2.8.1.5, "Data Exception Address Register (DEAR),"
effective address of the data access that results in an alignment, data TLB miss, or data storage interrupt.
5.6.4 MMU Control and Status Register 0 (MMUCSR0)
MMUCSR0, shown in Section 2.16.1, "MMU Control and Status Register 0
state of the MMU.
5.6.5 MMU Assist Registers (MAS)
The e200z3 uses MAS0–MAS4 and MAS6 SPRs to facilitate reading, writing, and searching the TLBs.
The e200z3 does not implement MAS5, because the tlbsx instruction only searches based on a single SPID
value.
MAS registers are described in
5.6.5.1 MAS Registers Summary
The fields of the MAS registers are summarized in
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57
MAS0 — TLBSEL
MAS1 VALID IPROT
MAS2
MAS3
MAS4 — TBSELD
MAS6 —
5.6.5.2 MAS Register Updates
Table 5-6 details the updates to each MAS register field for each update type.
5-14
Section 2.16.3, "TLB Configuration Registers (TLBnCFG)."
Section 2.16.4, "MMU Assist Registers (MAS0–MAS4, MAS6)."
— ESEL
— TID
EPN
RPN
— TIDSELD
SPID
Figure 5-6. MMU Assist Registers Summary
e200z3 Power Architecture Core Reference Manual, Rev. 2
Figure 5-6.
—
— TS TSIZ
—
— U0 U1 U2 U3
— TSIZED
is loaded with the
(MMUCSR0),"controls the
58 59 60 61 62
NV
—
VLE W I M G
UX SX UW SW UR SR
— VLED WD ID MD GD ED
—
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E
SAS