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2.12.4
Debug Status Register (DBSR)
DBSR, shown in
Figure
Hardware sets DBSR, and software reads and clears it by writing a 1 in any bit position that is to be cleared
and 0 in all other bit positions. The write data to the debug status register is not direct data, but a mask. A
1 causes the bit to be cleared, and a 0 has no effect. Debug status bits are set by debug events only while
internal debug mode is enabled or external debug mode is enabled. When debug interrupts are enabled
(MSR[DE] = 1, DBCR0[IDM] = 1, and DBCR0[EDM] = 0), a set bit in DBSR causes a debug interrupt
to be generated.
When debug interrupts are enabled (MSR[DE]=1, DBCR0[IDM]=1, and DBCR0[EDM]=0), a set bit in
DBSR other than MRR or VLES causes a debug interrupt. The debug interrupt handler clears DBSR bits
before returning to normal execution. The PowerPC VLE APU adds the DBSR[VLES] status bit to
indicate debug events occurring due to a PowerPC VLE instruction.
32
33
34 35
36
Field IDE UDE MRR ICMP BRT
Reset
R/W
48
49
52
Field RET
—
Reset
R/W
SPR
Table 2-22
provides field definitions for the debug status register.
Bits
Name
32
IDE
Imprecise debug event. Set if MSR[DE] = 0 and DBCR0[EDM] = 0 and a debug event causes its respective
debug status register bit to be set. IDE can also be set if DBCR0[EDM] = 1 and an imprecise debug event
occurs due to a DAC event on a load or store that is terminated with error, or if an ICMP event occurs in
conjunction with a SPE FP round exception.
33
UDE
Unconditional debug event. Set when an unconditional debug event occurs.
34–35
MRR
Most recent reset.
00 No reset since software last cleared these bits.
01 A hard reset occurred since software last cleared these bits.
1 x Reserved.
36
ICMP
Instruction complete debug event. Set if an instruction complete debug event occurs.
37
BRT
Branch taken debug event. Set if an branch taken debug event occurs.
38
IRPT
Interrupt taken debug event. Set if an interrupt taken debug event occurs.
Freescale Semiconductor
2-38, contains status on debug events and the most recent processor reset.
37
38
39
IRPT
TRAP
0001_0000_0000_0000
53
54
55
DEVT1 DEVT2 DCNT1 DCNT2 CIRPT CRET
0000_0000_0000_0000
Figure 2-38. DBSR Register
Table 2-22. DBSR Field Descriptions
e200z3 Power Architecture Core Reference Manual, Rev. 2
40
41
42
43
IAC1
IAC2
IAC3 IAC4 DAC1R DAC1W DAC2R
Read/Clear
56
57
58
59
—
Read/Clear
SPR 304
Description
Register Model
44
45
46
47
DAC2W
61
62
63
DAC_OFST
CNT1TRG
2-49
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