Freescale Semiconductor e200z3 Reference Manual page 221

Bits MSR Definition Reset Setting Non-Critical Interrupt Critical Interrupt Debug Interrupt
54 DE
55 FE1
58 IS
59 DS
62 RI
1
Conditionally cleared based on control bits in HID0
2
Cleared if the Debug APU is disabled, otherwise unaffected
4.8.1 Enabling and Disabling Exceptions
When a condition exists that may cause an exception to be generated, it must be determined whether the
exception is enabled for that condition.
• System reset exceptions cannot be masked.
• A machine check exception can occur only if the machine check enable, MSR[ME = 1, or if a
non-maskable interrupt is received. If ME = 0, the processor goes directly into checkstop state
when a machine check exception condition occurs, unless the machine check is the result of a
non-maskable interrupt. Individual machine check exceptions (other than non-maskable interrupts)
can be enabled and disabled through HID0 bits.
• Asynchronous, maskable non-critical exceptions (such as the external input and decrementer) are
enabled by setting MSR[EE]. When EE = 0, recognition of these exception conditions is delayed.
EE is cleared automatically when a non-critical or critical interrupt is taken to mask further
recognition of conditions causing those exceptions.
• Asynchronous, maskable critical exceptions (such as critical input and watchdog timer) are
enabled by setting MSR[CE]. When CE = 0, recognition of these exception conditions is delayed.
CE is cleared automatically when a critical interrupt is taken to mask further recognition of
conditions causing those exceptions. In addition MSR[RI] is cleared to indicate that the CSRR0/1
registers contain information essential to exception recovery.
• Synchronous and asynchronous debug exceptions are enabled by setting MSR[DE]. If DE = 0,
recognition of these exception conditions is masked. DE is cleared automatically when a debug
interrupt is taken to mask further recognition of conditions causing those exceptions.
"Debug Support,"
• The floating-point unavailable exception can be prevented by setting MSR[FP] (although the
e200z3 generates an unimplemented instruction exception instead).
4.8.2 Returning from an Interrupt Handler
The Return from Interrupt (rfi), Return from Critical Interrupt (rfci) and Return from Debug Interrupt
(rfdi) instructions perform context synchronization by allowing instructions issued earlier to complete
before returning to the interrupted process. In general, execution of rfi, rfci, or rfdi ensures the following:
Freescale Semiconductor
Table 4-33. MSR Setting Due to Interrupt (continued)
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gives details on individual control of debug exceptions.
e200z3 Power Architecture Core Reference Manual, Rev. 2
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Interrupts and Exceptions
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Chapter 9,
4-33