Freescale Semiconductor e200z3 Reference Manual page 231

See Table 5-6 for a complete description of MAS register updates on various exception conditions.
5.3.3 The G Bit (of WIMGE)
The G bit provides protection from bus accesses that could be canceled due to an exception on a prior
uncompleted instruction.
If G = 1 (guarded), these types of accesses must stall until the exception status of any instructions in
progress is known. If G = 0 (unguarded), these accesses may be issued to the bus regardless of the
completion status of other instructions. Because the core does not make requests for load or store
instructions until it is known that prior instructions will complete without exceptions, the G bit is
essentially ignored. Proper operation always occurs to guarded storage.
5.3.4 TLB Entry Field Summary
Table 5-3 summarizes the fields of e200z3 TLB entries. Note that all of these fields are defined at the
Freescale Book E level.
Field
V Valid bit for entry
TS Translation address space (compared with AS bit of the current access)
TID[0–7] Translation ID (compared with PID0 or TIDZ (all zeros))
EPN[0–19] Effective page number (compared with effective address)
RPN[0–19] Real page number (translated address)
Freescale Semiconductor
MAS0
ESEL
NV
TLB Miss (TLB Error Interrupt
Figure 5-5. Victim Selection
Table 5-3. TLB Entry Bit Fields for e200z3
e200z3 Power Architecture Core Reference Manual, Rev. 2
On tlbwe, SelectsEntry
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Description
Memory Management Unit
5-9