Freescale Semiconductor e200z3 Reference Manual page 350

Debug Support
9.5.5.1 OnCE Status Register (OSR)
Status information regarding the state of the CPU is latched into the OSR when the OnCE controller state
machine enters the Capture-IR state. When OnCE operation is enabled, this information is provided on the
j_tdo output in serial fashion when the Shift-IR state is entered following a Capture-IR. Information is
shifted out least-significant bit first.
0 1
Field MCLK ERR
Table 9-6 describes OnCE status register bits.
.
Bits Name
0 MCLK m_clk status bit. Reflects the logic level on the jd_mclk_on input signal after capture by j_tclk .
0 Inactive state
1 Active state
1 ERR Error. Used to indicate that an error condition occurred during attempted execution of the last single-stepped
instruction (Go+NoExit with CPUSCR or no register selected in OCMD), and that the instruction may not have
executed properly. This can occur if an interrupt (all classes including external, critical, machine check,
storage, alignment, program, TLB, and so on) occurs while attempting to perform the instruction single-step.
In this case, CPUSCR contains information related to the first instruction of the interrupt handler, and no
portion of the handler will have executed.
CHKSTOP Checkstop mode. Reflects the logic level on the CPU p_chkstop output after capture by j_tclk .
2
Reset mode. Reflects the inverted logic level on the CPU p_reset_b input after capture by j_tclk .
3 RESET
4 HALT Halt mode. Reflects the logic level on the CPU p_halted output after capture by j_tclk .
5 STOP Stop mode. Reflects the logic level on the CPU p_stopped output after capture by j_tclk .
6 DEBUG Debug mode. Set once the CPU is in debug mode. It is negated once the CPU exits debug mode (even during
a debug session).
7 WAIT Waiting Mode (e200z335 only)
This bit reflects the logic level on the CPU p_waiting output after capture by j_tclk.
Reserved, set to 0 on e200z3.
8 — Reserved, set to 0 for 1149.1 compliance
9 — Reserved, set to 1 for 1149.1 compliance
9.5.5.2 OnCE Command Register (OCMD)
The OnCE command register (OCMD) is a 10-bit shift register that receives its serial data from the TDI
pin and serves as the instruction register (IR). It holds the 10-bit commands to be used as input for the
OnCE decoder. OCMD is shown in
state. It contains fields for controlling access to a resource, as well as controlling single-step operation and
exit from OnCE mode.
9-18
2 3
CHKSTOP RESET HALT
Figure 9-5. OnCE Status Register (OSR)
Table 9-6. OSR Field Descriptions
Figure 9-5. It is updated when the TAP controller enters the Update-IR
e200z3 Power Architecture Core Reference Manual, Rev. 2
4 5 6
STOP DEBUG
Description
7 8 9
WAIT 0 1
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