Freescale Semiconductor e200z3 Reference Manual page 334

Debug Support
Software debug facilities are enabled by setting the internal debug mode bit, DBCR0[IDM]. If
DBCR0[IDM] is set, debug events can occur and can be enabled to record exceptions in the DBSR. If
enabled by MSR[DE], these exceptions cause debug interrupts. If DBCR0[IDM] and DBCR0[EDM]
(EDM represents the external debug mode bit) are cleared, no debug events occur and no status flags are
set in DBSR unless already set. In addition, if DBCR0[IDM] is cleared (or is overridden by DBCR0[EDM]
being set and DBERC0 indicating no resource is "owned" by software), no debug interrupts can occur,
regardless of the contents of DBSR. A software debug interrupt handler can access all system resources
and perform the necessary functions appropriate for system debugging.
9.2.1.1 PowerPC Book E Compatibility
The core implements a subset of the PowerPC Book E internal debug features. The following restrictions
on functionality are present:
• Instruction address compares do not support compare on physical (real) addresses.
• Data address compares do not support compare on physical (real) addresses.
• Data value compares are not supported (but are supported in e200z335).
9.2.2 Additional Debug Facilities
In addition to the debug functionality defined in Book E, the core provides the capability to link instruction
and data breakpoints. The core also provides a configurable debug event counter to allow debug exception
generation and a sequential breakpoint control mechanism.
The core also defines two new debug events (critical interrupt taken and critical return) for debugging
around critical interrupts.
In addition, the core implements the debug auxiliary processing unit (APU) which, when enabled, allows
debug interrupts to use a dedicated set of save/restore registers (DSRR0 and DSRR1) to save state
information when a debug interrupt occurs and restore this state information at the end of a debug interrupt
handler with the rfdi instruction.
9.2.3 Hardware Debug Facilities
The core contains facilities that allow for external test and debugging. A modified IEEE 1149.1 control
interface is used to communicate with core resources. This interface is implemented through a standard
1149.1 TAP (test access port) controller.
By using public instructions, the external debugger can freeze or halt the core, read and write internal state
and debug facilities, single-step instructions, and resume normal execution.
Hardware debug is enabled by setting the external debug mode enable bit (DBCR0[EDM]). Setting
DBCR0[EDM] overrides the internal debug mode enable bit DBCR0[IDM] unless resources are provided
back to software via the settings in DBERC0. If the hardware debug facility is enabled, software is blocked
from modifying the debug facilities. In addition, because resources are owned by the hardware debugger,
inconsistent values may be present if software attempts to read debug-related resources.
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e200z3 Power Architecture Core Reference Manual, Rev. 2
Freescale Semiconductor