Freescale Semiconductor e200z3 Reference Manual page 284

External Core Complex Interfaces
Table 7-8. Big-and Little-Endian Storage (64-Bit GPR Contains 'A B C D E F G H') (continued)
Program Size
and Byte Offset
L. E. Word @1101
+ 0 0 0 0
(next dword)
L. E. Word @1110
+ 0 0 0 0
(next dword)
L. E. Word @1111
+ 0 0 0 0
(next dword)
B.E. Double word
L.E. Double word
1
These misaligned transfers drive size according to the size of the power of two aligned containers in which the byte
strobes are asserted.
Table 7-9 describes the transfer control signals.
Table 7-9. Descriptions of Signals for Transfer Control Signals
Signal I/O
p_[d,i]_hready I Transfer ready. Indicates whether a requested transfer operation has completed. An external device
asserts p_[d,i]_hready to terminate the transfer. p_hresp[2:0] indicate the transfer status.
State
Meaning
p_hresp[2:0]
I Transfer response. Indicate status of a terminating transfer.
000 OKAY—Transfer terminated normally.
001 ERROR—Transfer terminated abnormally. See note for assertion.
010 Reserved (RETRY not supported in AHB-Lite protocol)
011 Reserved (SPLIT not supported in AHB-Lite protocol)
100 XFAIL—Exclusive store failed (stwcx. did not complete successfully). See note for assertion.
(Signaled to the CPU using the p_xfail_b internal signal. See
101–111 Reserved
Timing Assertion—ERROR and XFAIL are required to be 2-cycle responses that must be signaled one
7-16
Even Double Word— 0
HSIZE
A(3:0)
(1:0)
B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7
1 1 0 1 1 0 — — — — — — — — — — — — —
0 0 E — — — — — — — — — — — — — — —
1 1 1 0 1 0 — — — — — — — — — — — — — —
0 1 F E — — — — — — — — — — — — — —
1 1 1 1 1 0 — — — — — — — — — — — — — — —
1 0 G F
- 0 0 0 1 1 A B
- 0 0 0 1 1 H G
Asserted—A requested transfer operation has completed. An external device asserts
p_[d,i]_hready to terminate the transfer.
Negated—A requested transfer operation has not completed.
cycle before assertion of p_[d,i]_hready and must remain unchanged during the cycle
p_[d,i]_hready is asserted. The XFAIL response is signaled to the CPU using the
p_xfail_b internal signal.
e200z3 Power Architecture Core Reference Manual, Rev. 2
E — — — — — — — — — — — — —
C D E F G H — — — — — — — —
F E D C B A — — — — — — — —
Signal Description
0dd Double Word—1
H G
H
Table 7-26.)
Freescale Semiconductor
F
G
H