Freescale Semiconductor e200z3 Reference Manual page 316

External Core Complex Interfaces
Figure 7-19 shows functional timing for a burst read with wait-state transfer where the second beat to addr
x+8 is retracted and replaced with a new burst transfer.
m_clk
p_htrans
p_addr,p_hprot
p_hsize,
p_hbstrb, etc
p_hburst
p_hunalign
p_hwrite
p_hrdata
p_hwdata
p_hready
p_hresp
Figure 7-19. Burst Read with Wait-State Transfer, Retraction
The first cycle of the burst incurs a single wait state, and the burst is replaced by another burst.
7-48
Burst Read with wait-state
1 2
seq
nonseq nonseq
addr x addr x+8 addr y
okay okay
e200z3 Power Architecture Core Reference Manual, Rev. 2
3 4
seq
addr y+8
incr
data x data y
okay okay
5 6 7
seq idle
addr y+16
data y+8 data y+16
okay okay
Freescale Semiconductor