Freescale Semiconductor e200z3 Reference Manual page 92

Register Model
Limited support is provided for any combination of IAC[1–4] with DAC[1–2] (linked or unlinked).
Due to pipelining and detection of IAC events early in the pipeline and DAC events late in the pipeline,
no guarantee is made on the exact instruction boundary that a debug exception is generated when IAC and
DAC events are combined for counting. This also applies when counter 1 is triggered by counter 2, and a
combination of IAC and DAC events is enabled for the counters, even if only one of these types is enabled
for a particular counter. In general, when an IAC event logically follows a DAC event within several
instructions, it cannot be recognized immediately because the DAC event may not be generated in the
pipeline at the time the IAC appears. Thus, the counter may not decrement to zero for the IAC event until
after the instruction with the IAC (and perhaps several additional instructions) proceeds down the
execution pipeline. The instruction boundary where the debug exception is actually generated typically
follows the IAC by up to several instructions.
Note that the counters operate regardless of whether counters are enabled to generate debug exceptions.
If counter 2 is used to trigger counter 1, counter 2 events should not normally be enabled in DBCR0 and
are not blocked.
Multiple IAC or DAC events are not counted during an lmw or stmw
instruction, and no count occurs if either is interrupted by a critical input or
external input interrupt before completion.
32
Field DEVT1C1
Reset
R/W
40
Field DAC1WC1
Reset
R/W
48
IAC1C2
Reset
R/W
56
DEVT1T1
Reset
R/W
SPR
2-44
NOTE
33 34
DEVT2C1 ICMPC1 IAC1C1
41 42
DAC2RC1 DAC2WC1 IRPTC1
49 50
IAC2C2 IAC3C2 IAC4C2
57 58
DEVT2T1 IAC1T1 IAC3T1
Figure 2-36. DBCR3 Register
e200z3 Power Architecture Core Reference Manual, Rev. 2
35 36 37
IAC2C1 IAC3C1
All zeros
R/W
43 44 45
RETC1 DEVT1C2 DEVT2C2
All zeros
R/W
51 52 53
DAC1RC2 DAC1WC2 DAC2RC2
All zeros
R/W
59 60 61
DAC1RT1 DAC1WT1
All zeros
R/W
SPR 561
38 39
IAC4C1 DAC1RC1
46 47
ICMPC2
54 55
DAC2WC2
62 63
CNT2T1 CONFIG
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