Freescale Semiconductor e200z3 Reference Manual page 35

Additional Features
• OnCe/Nexus 1/Nexus
2+ control logic
• AMBA AHB-Lite bus
• SPE (SIMD)
• VLE
• Embedded scalar/
vector floating-point
• Power management
• Time base/ decrementer
counter
• Clock multiplier
Execute Stage
32 GPRs
Four-cycle,
(64-Bit) single-path
execute stage
with overlapped
execution and
feed forwarding
CR
XER
LR
CTR
Write-Back Stage
SPRs
The e200z3 is a single-issue, 32-bit, Power ISA–compliant design with 64-bit, general-purpose registers
(GPRs).
Instructions of the signal processing extension (SPE) category, as well as of the embedded vector and
scalar floating-point categories, are provided to support real-time integer and single-precision embedded
floating-point operations using the GPRs. The e200z3 does not support Power ISA floating-point
instructions in hardware but traps them so they can be emulated by software.
All arithmetic instructions that execute in the core operate on data in the GPRs, which have been extended
to 64 bits to support vector instructions defined by the SPE and embedded vector floating-point categories.
These instructions operate on a vector pair of 16- or 32-bit data types and deliver vector and scalar results.
The e200z3 contains a memory management unit (MMU). A Nexus Class 3 module is also integrated in
the e200z3 and a Nexus Class 2+ module is integrated in the e200z335.
The e200z3 platform is specified in such a way that functional units can be added or removed. The e200z3
can be configured with a powerful vectored interrupt controller and one or more IP slave interfaces, as well
as support for configured memory units.
Freescale Semiconductor
Instruction/Control Unit
Instruction Buffer
(7 instructions)
Decode
Stage
Single-instruction, in-order dispatch
Execution Units
Embedded
Scalar FPU
+ x ÷
Embedded
Vector FPU
+ x ÷
VLE
Single-Instruction, In-Order Write Back
e200z335
Figure 1-2.
e200z3 Power Architecture Core Reference Manual, Rev. 2
Fetch Unit
Two/Four
instructions
Program Counter
Two-Cycle
Fetch Stage
Branch Processing Unit
+
EA Calc
8-Entry Branch
Target Buffer
SPE Branch
Unit Unit
+ x ÷
Load/Store Address
Integer
Unit
Unit
+ x ÷ + EA Calc
Optional
Extension
Address
Block Diagram
e200z335 Core Complex Overview
Unified Memory Unit
Software-Managed
L1 Unified MMU
8-Entry
Fully Associative
•
•
•
TLB
4-Kbyte to
4-MGbyte page sizes
MAS
Registers
Instruction Bus Interface Unit
32 64
Data Control
Data Bus Interface Unit
32 64
Data Control
N
N
1-3