Freescale Semiconductor e200z3 Reference Manual page 217

— Synchronous, maskable, recoverable: Interrupt taken debug event. The machine is in a
recoverable state due to the state of the machine at the context switch triggering this event.
• Instruction-based interrupts. These interrupts are further organized by the point in instruction
processing in which they generate an exception.
— Instruction fetch: Instruction storage, instruction TLB, and instruction address compare debug
exceptions.
Once these types of exceptions are detected, the excepting instruction is tagged. When the
excepting instruction is next to begin execution and a recoverable state has been reached, the
interrupt is taken. If an event prior to the excepting instruction causes a redirection of
execution, the instruction fetch exception is discarded (but may be encountered again).
— Instruction dispatch/execution: Program, system call, data storage, alignment, floating-point
unavailable, SPE unavailable, data TLB, SPE floating-point data, SPE floating-point round,
debug (trap, branch taken, return) interrupts.
Determined during decode or execution of an instruction. The exception remains pending until
all instructions before the exception-causing instruction complete. The interrupt is then taken
without completing the exception-causing instruction. If completing previous instructions
causes an exception, that exception takes priority over the pending instruction
dispatch/execution exception, which is discarded (but may be encountered again when
instruction processing resumes).
— Post-instruction execution: Debug (data address compare, instruction complete) interrupt
Generated following execution and completion of an instruction while the event is enabled. If
executing the instruction produces conditions for another type of exception with higher
priority, that exception is taken and the post-instruction exception is discarded for the
instruction (but may be encountered again when instruction processing resumes).
4.7.1 Interrupt Priorities
Interrupts are prioritized as described in
affects their priority. Non-maskable exceptions such as reset and machine check may occur at any time and
are not delayed even if an interrupt is being serviced; thus, state information for any interrupt may be lost.
Reset and most machine checks are non-recoverable.
Priority Exception
0 System reset
1 Machine check
2 —
Freescale Semiconductor
Table 4-32. Some exceptions may be masked or imprecise, which
Table 4-32. e200z3 Exception Priorities
Asynchronous Exceptions
Assertion of p_reset_b , watchdog timer reset control, or debug reset control
Assertion of p_mcp_b , exception on fetch of first instruction of an interrupt
handler, bus error on buffered store , bus error (XTE) with MSR[EE]=0 and
current MSR[ME]=1, or assertion of p_nmi_b
—
e200z3 Power Architecture Core Reference Manual, Rev. 2
Interrupts and Exceptions
Cause IVOR
none
1
—
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