Freescale Semiconductor e200z3 Reference Manual page 53

– Processor identification register (PIR). A read-only register to distinguish the processor
from other processors in the system.
— Storage control registers
– Process ID register (PID0, also referred to as PID). Indicates the current process or task
identifier. The MMU uses it as an extension to the effective address, and the external Nexus
2 module uses it for ownership trace message generation. PowerPC Book E allows multiple
PIDs; the e200z3 implements only one.
— Interrupt registers
– Data exception address register (DEAR). After most data storage interrupts (DSIs), or on an
alignment interrupt or data TLB interrupt, DEAR is set to the effective address (EA)
generated by the faulting instruction.
– SPRG0–SPRG7, USPRG0. For software use. See
(SPRG0–SPRG7 and USPRG0),"
user-mode access to the SPRG3 register. Book E defines access to SPRG3 as
implementation-dependent.
– Exception syndrome register (ESR). A syndrome to differentiate between the different kinds
of exceptions that can generate the same interrupt.
– Interrupt vector prefix register (IVPR) and interrupt-specific interrupt vector offset registers
(IVORs). Provide the address of the interrupt handler for different classes of interrupts.
– Save/restore register 0 (SRR0). Saves machine state on a non-critical interrupt and contains
the address of the instruction at which execution resumes when an rfi instruction executes
at the end of a non-critical-class interrupt handler routine.
– Save/restore register 1 (SRR1). Saves machine state from the MSR on non-critical
interrupts and restores machine state when rfi executes.
– Critical save/restore register 0 (CSRR0). Saves machine state on a critical interrupt and
contains the address of the instruction at which execution resumes when an rfci instruction
executes at the end of a critical-class interrupt handler routine.
– Critical save/restore register 1 (CSRR1). Saves machine state from the MSR on critical
interrupts and restores machine state when rfci executes.
— Debug facility registers
– Debug control registers (DBCR0–DBCR2). Provide control for enabling and configuring
debug events.
– Debug status register (DBSR). Contains debug event status.
– Instruction address compare registers (IAC1–IAC4). Contain addresses and/or masks to
specify instruction address compare debug events.
– Data address compare registers (DAC1–DAC2). Contain addresses and/or masks to specify
data address compare debug events.
– Data value compare registers (DVC1-DVC2). Contain data values to specify data value
compare debug events.
— Timer registers
Freescale Semiconductor
for details on these registers. The e200z3 does not allow
e200z3 Power Architecture Core Reference Manual, Rev. 2
Section 2.10, "Software-Use SPRs
Register Model
2-5