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Freescale Semiconductor e200z3 Reference Manual page 265

Power architecture core

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Table 6-6. SPE Complex Integer Instruction Timing (continued)

Instruction

evmwlssianw

evmwlumi

evmwlumia

evmwlumiaaw

evmwlumianw

evmwlusiaaw

evmwlusianw

evmwsmf

evmwsmfa

evmwsmfaa

evmwsmfan

evmwsmi

evmwsmia

evmwsmiaa

evmwsmian

evmwssf

evmwssfa

evmwssfaa

evmwssfan

evmwumi

evmwumia

evmwumiaa

evmwumian

evsubfsmiaaw

evsubfssiaaw

evsubfumiaaw

evsubfusiaaw

6.7.1.4

Vector Floating-Point APU Instruction Timing

Timings for embedded vector single-precision floating-point instructions are shown in

number of stall cycles for evfsdiv is (latency) cycles.

Freescale Semiconductor

Latency Throughput

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

e200z3 Power Architecture Core Reference Manual, Rev. 2

Instruction Pipeline and Execution Timing

Comments

Table

6-4. The

6-27

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