Freescale Semiconductor e200z3 Reference Manual page 101

Bit(s) Name
8 IAC1
9 IAC2
10 IAC3
11 IAC4
12 DAC1
13 —
14 DAC2
15 —
16 RET
17:20 —
21 DEVT1
Freescale Semiconductor
Table 2-23. DBERC0 Bit Definitions (continued)
Instruction Address Compare 1 Debug Event
0 - Event owned by hardware debug. No mtspr access by software to IAC1 control and status
fields.
1 - Event owned by software debug. DBCR0[IAC1] and DBSR[IAC1] are software
readable/writeable.
Instruction Address Compare 2 Debug Event
0 - Event owned by hardware debug. No mtspr access by software to IAC2 control and status
fields.
1 - Event owned by software debug. IAC2 control and status fields are software
readable/writeable.
Instruction Address Compare 3 Debug Event
0 - Event owned by hardware debug. No mtspr access by software to IAC3 control and status
fields.
1 - Event owned by software debug. IAC3 control and status fields are software
readable/writeable.
Instruction Address Compare 4 Debug Event
0 - Event owned by hardware debug. No mtspr access by software to IAC4 control and status
fields.
1 - Event owned by software debug. IAC4 control and status fields are software
readable/writeable.
Data Address Compare 1 Debug Event
0 - Event owned by hardware debug. No mtspr access by software to DAC1 control and
status fields.
1 - Event owned by software debug. DAC1 control and status fields are software
readable/writeable.
Reserved
Data Address Compare 2 Debug Event
0 - Event owned by hardware debug. No mtspr access by software to DAC2 control and
status fields.
1 - Event owned by software debug. DAC2 control and status fields are software
readable/writeable.
Reserved
Return Debug Event
0 - Event owned by hardware debug. No mtspr access by software to DBCR0[RET] or
DBSR[RET] fields.
1 - Event owned by software debug. DBCR0[RET] and DBSR[RET] are software
readable/writeable.
Reserved
External Debug Event 1 Debug Event
0 - Event owned by hardware debug. No mtspr access by software to DBCR0[DEVT1] or
DBSR[DEVT1] fields.
1 - Event owned by software debug. DBCR0[DEVT1] and DBSR[DEVT1] are software
readable/writeable.
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Register Model
2-53