Freescale Semiconductor e200z3 Reference Manual page 279

to address 0 is connected to B0 (p_h{r,w}data[7:0]) and the byte corresponding to address 7 is connected
to B7 (p_h{r,w}data[63:56]). The CPU internally permutes read data as required for the endian mode of
the current access. Assertion of p_[d,i]_hunalign indicates misaligned transfers and that byte strobes do
not correspond exactly to size and low-order address bits.
Table 7-6. Descriptions of Signals for Byte Lane Specification
Signal I/O
p_[d,i]_hunalign O Unaligned access. Indicates whether the current access is misaligned.
Meaning
Timing The timing of this signal is approximately the same as address timing.
p_[d,i]_hbstrb[7:0] O Byte strobes. Indicate the bytes selected for the current transfer. For a misaligned access, the current
transfer may not include all bytes defined by the size and low-order address signals. For aligned
transfers, the byte strobe signals correspond to the bytes that size and low-order address signals
define. The relationships of byte addresses to the byte strobe signals are as follows.
Memory byte address
Table 7-7 lists all data transfer permutations. Note that misaligned data requests that cross a 64-bit
boundary are broken into two bus transactions, and the address value and size encoding for the first transfer
are not modified. The table is arranged in a big-endian fashion, but the active lanes are the same regardless
of the endian-mode of the access. The core performs the proper byte routing internally based on
endianness.
Program Size
and Byte Offset
Byte @000
Byte @001
Byte @010
Byte @011
Byte @100
Freescale Semiconductor
State Asserted—Asserted for misaligned data accesses and for misaligned instruction accesses
from VLE pages. Normal Book E instruction pages are always aligned. When
p_[d,i]_hunalign is asserted, the p_[d,i]_hbstrb[7:0] byte strobe signals indicate the
selected bytes involved in the current portion of the misaligned access, which may not
include all bytes defined by the size and low-order address signals. Aligned transfers
also assert the byte strobes, but in a manner corresponding to size and low-order
address bits.
Negated—No misaligned data access is occurring.
Wired to p_h{r,w}data bits
000
001
010
011
100
101
110
111
Table 7-7. Byte Strobe Assertion for Transfers
HSIZE
A(2:0)
[1:0]
B0
0 0 0 0 0 X
0 0 1 0 0 —
0 1 0 0 0 —
0 1 1 0 0 —
1 0 0 0 0 —
e200z3 Power Architecture Core Reference Manual, Rev. 2
Signal Description
Corresponding byte strobe signal
7:0
15:8
23:16
31:24
39:32
47:40
55:48
63:56
Data Bus Byte Strobes
B1 B2 B3 B4 B5
— — — — —
X — — — —
— X — — —
— — X — —
— — — X —
External Core Complex Interfaces
p_[d,i]_hbstrb[0]
p_[d,i]_hbstrb[1]
p_[d,i]_hbstrb[2]
p_[d,i]_hbstrb[3]
p_[d,i]_hbstrb[4]
p_[d,i]_hbstrb[5]
p_[d,i]_hbstrb[6]
p_[d,i]_hbstrb[7]
1
HUNALIGN
B6 B7
— — 0
— — 0
— — 0
— — 0
— — 0
7-11