Freescale Semiconductor e200z3 Reference Manual page 274

External Core Complex Interfaces
Signal Name I/O Reset
p_halt I
p_halted O
p_stop I
p_stopped O
p_ude I
p_devt1 I
p_devt2 I
jd_en_once I
jd_debug_b O
jd_de_b I
jd_de_en O
jd_mclk_on I
jd_watchpt[0:7]
O
nex_mcko O
nex_rdy_b O
nex_evto_b O
nex_evt i_ b I
nex_mdo[n:0]
O
nex_mseo_b[1:0]
O
j_trst_b I
j_tclk I
j_tms I
j_tdi I
j_tdo O
j_tdo_en O
j_tst_log_rst O
j_capture_ir O
j_update_ir O
7-6
Table 7-1. Interface Signal Definitions (continued)
CPU halt request
0 CPU halted
CPU stop request
0 CPU stopped
CPU Debug Event Signals
Unconditional debug event
Debug event 1 input
Debug event 2 input
Debug/Emulation Support Signals (Nexus 1/OnCE)
Enable full OnCE operation
1 Processor entered debug session
Debug request
0 Active-high output enable for DE_b open-drain IO cell
System clock controller actively toggling m_clk
0 Address watchpoint occurred
Development Support Signals (Nexus 3)
Nexus3 clock output
Nexus3 ready output
Nexus3 event-out output
Nexus3 event-in input
Nexus3 message data output
Nexus3 message start/end output
JTAG-Related Signals
JTAG test reset from pad
JTAG test clock from pad
JTAG test mode select from pad
JTAG test data input from pad
0 JTAG test data out to master controller or pad
0 Enables TDO output buffer
0 Test-logic-reset state of JTAG controller
0 Capture_IR state of JTAG controller
0 Update_IR state of JTAG controller
e200z3 Power Architecture Core Reference Manual, Rev. 2
Definition
Freescale Semiconductor