Freescale Semiconductor e200z3 Reference Manual page 65

Table 2-9 describes SPEFSCR fields.
Bits Name
32 SOVH Summary integer overflow high. Set whenever an instruction sets OVH and remains set until it is cleared by
an mtspr specifying the SPEFSCR.
33 OVH Integer overflow high. Set whenever an integer or fractional SPE instruction signals an overflow in the upper
half of the result.
34 FGH Embedded floating-point guard bit high. For use by the floating-point round exception handler. It is cleared by
a floating-point data exception for the high elements. FGH corresponds to the high element result. FGH is
cleared by a scalar floating-point instruction.
35 FXH Embedded floating-point sticky bit high. Supplied for use by the floating-point round exception handler.
Zeroed if a floating-point data exception occurred for the high elements. FXH corresponds to the high element
result. FXH is cleared by a scalar floating point instruction.
36 FINVH Embedded floating-point invalid operation/input error high.
In mode 0, set if the A or B high element operand of a floating-point instruction is Infinity, NaN, or Denorm, or
if the operation is a divide and the high element dividend and divisor are both 0.
In mode 1, FINVH is set on an IEEE754 invalid operation (IEEE754-1985 sec7.1) in the high element. Cleared
by a scalar floating-point instruction.
37 FDBZH Embedded floating-point divide by zero high. Set when a floating-point divide instruction executes with a high
element divisor of 0 and the high element dividend is a finite non-zero number. Cleared by a scalar
floating-point instruction.
38 FUNFH Embedded floating-point underflow high. Set when the execution of a floating-point instruction results in an
underflow in the high element. FUNFH is cleared by a scalar floating-point instruction.
39 FOVFH Embedded floating-point overflow high. Set when the execution of a floating-point instruction results in an
overflow in the high element. Cleared by a scalar floating point instruction.
40–41 — Reserved, should be cleared.
42 FINXS Embedded floating-point inexact sticky flag. Set under one of the following conditions:
• The execution of a floating-point instruction delivers an inexact result for either the low or high element and
no floating-point data exception is taken for either element
• A floating-point instruction causes overflow (FOVF=1 or FOVFH=1), but floating-point overflow exceptions
are disabled (FOVFE=0)
• A floating-point instruction results in underflow (FUNF=1 or FUNFH=1), but floating-point underflow
exceptions are disabled (FUNFE=0) and no floating-point data exception occurs.
FINXS remains set until it is cleared by an mtspr specifying SPEFSCR.
43 FINVS Embedded floating-point invalid operation sticky flag. Set when a floating-point instruction sets FINVH or
FINV. FINVS remains set until it is cleared by an mtspr instruction specifying SPEFSCR.
44 FDBZS Embedded floating-point divide by zero sticky flag. Set when a floating-point divide instruction sets FDBZH
or FDBZ. FDBZS remains set until it is cleared by an mtspr specifying SPEFSCR.
45 FUNFS Embedded floating-point underflow sticky flag. Set when a floating-point instruction sets FUNFH or FUNF.
FUNFS remains set until it is cleared by an mtspr specifying SPEFSCR.
46 FOVFS Embedded floating-point overflow sticky flag. Set when a floating-point instruction sets FOVFH or FOVF.
FOVFS remains set until it is cleared by an mtspr specifying SPEFSCR.
Freescale Semiconductor
Table 2-9. SPEFSCR Field Descriptions
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Register Model
2-17