Freescale Semiconductor e200z3 Reference Manual page 198

Interrupts and Exceptions
IVOR Number
IVOR11
IVOR12
IVOR13
IVOR14
IVOR15
IVOR16–IVOR31
IVOR32
IVOR33
IVOR34
4.6 Interrupt Definitions
The following sections describe interrupts as they are implemented on the e200z3.
4.6.1 Critical Input Interrupt (IVOR0)
A critical input exception is signaled to the processor by the assertion of the critical interrupt pin
(p_critint_b). When the e200z3 detects the exception, if critical interrupts are enabled (MSR[CE] = 1), the
e200z3 takes the critical input interrupt. The p_critint_b input is a level-sensitive signal expected to remain
asserted until the e200z3 acknowledges the interrupt. If p_critint_b is negated early, recognition of the
interrupt request is not guaranteed. After the e200z3 begins execution of the critical interrupt handler, the
system can safely negate p_critint_b.
A critical input interrupt may be delayed by other higher priority exceptions or if MSR[CE] is cleared
when the exception occurs.
Table 4-9 lists register settings when a critical input interrupt is taken.
Register
CSRR0 Set to the effective address of the instruction that the processor would have attempted to execute next if no
exception conditions were present.
CSRR1 Set to the contents of the MSR at the time of the interrupt.
MSR UCLE 0
SPE 0
WE 0
CE 0
EE 0
ESR Unchanged
4-10
Table 4-8. IVOR Assignments (continued)
SPR
411 Fixed-interval timer interrupt
412 Watchdog timer interrupt
413 Data TLB error
414 Instruction TLB error
415 Debug
— Reserved for future architectural use
-Specific IVORs (Defined by the EIS)
528 SPE APU unavailable
529 SPE floating-point data exception
530 SPE floating-point round exception
Table 4-9. Critical Input Interrupt Register Settings
Setting Description
PR 0
FP 0
ME —
FE0 0
e200z3 Power Architecture Core Reference Manual, Rev. 2
Interrupt Type
1
DE —/0
FE1 0
IS 0
DS 0
2
RI 0
Freescale Semiconductor