Freescale Semiconductor e200z3 Reference Manual page 56

Register Model
32 36 37
Field — UCLE SPE
Reset
R/W
1
RI bit in e200z335 only
MSR fields are described in
Bits Name
32–36 — Reserved, should be cleared.
37 UCLE User cache lock enable.
0 Execution of the cache locking instructions is disabled in user mode (MSR[PR] = 1). Instead, the data storage
interrupt is taken, and ILK or DLK is set in the ESR.
1 Execution of the cache lock instructions is enabled in user mode.
38 SPE SPE available.
0 Execution of SPE APU vector instructions is disabled. Instead, the SPE unavailable exception is taken, and
ESR[SPE] is set.
1 Execution of SPE APU vector instructions is enabled.
39–44 — Reserved, should be cleared.
45 WE Wait state (power management) enable. Defined as optional by Book E and implemented in the e200z3.
0 Power management is disabled.
1 Power management is enabled. The processor can enter a power-saving mode when additional conditions
are present. The mode chosen is determined by HID0[DOZE,NAP,SLEEP], described in
"Hardware Implementation-Dependent Register 0
46 CE Critical interrupt enable
0 Critical input and watchdog timer interrupts are disabled.
1 Critical input and watchdog timer interrupts are enabled.
47 — Preserved.
48 EE External interrupt enable
0 External input, decrementer, and fixed-interval timer interrupts are disabled.
1 External input, decrementer, and fixed-interval timer interrupts are enabled.
49 PR Problem state.
0 The processor is in supervisor mode, can execute any instruction, and can access any resource (for example,
GPRs, all SPRs, and the MSR).
1 The processor is in user mode, cannot execute any privileged instruction, and cannot access any privileged
resource.
50 FP Floating-point available.
0 Floating-point unit is unavailable. The processor cannot execute floating-point instructions, including
floating-point loads, stores, and moves. (An FP unavailable interrupt is generated on attempted execution of
floating-point instructions).
1 Floating-point unit is available. The processor can execute floating-point instructions. (Note that for the
e200z3, the floating-point unit is not supported; an unimplemented operation exception is generated for
attempted execution of floating-point instructions when FP is set).
2-8
38 39 44 45 46 47
— WE CE — EE PR FP ME FE0 — DE FE1
Figure 2-2. Machine State Register (MSR)
Table 2-1.
Table 2-1. MSR Field Descriptions
e200z3 Power Architecture Core Reference Manual, Rev. 2
48 49 50 51 52 53 54
All zeros
R/W
Description
(HID0)."
55 56 57 58 59 60 63
1
— IS DS — RI
Section 2.13.1,
Freescale Semiconductor