Freescale Semiconductor e200z3 Reference Manual page 93

Table 2-20 provides field definitions for DBCR3
Bits Name
32 DEVT1C1 External debug event 1 count 1 enable.
0 Counting DEVT1 debug events by counter 1 is disabled.
1 Counting DEVT1 debug events by counter 1 is enabled.
33 DEVT2C1 External debug event 2 count 1 enable.
0 Counting DEVT2 debug events by counter 1 is disabled.
1 Counting DEVT2 debug events by counter 1 is enabled.
34 ICMPC1 Instruction complete debug event count 1 enable.
0 Counting ICMP debug events by counter 1 is disabled.
1 Counting ICMP debug events by counter 1 is enabled.
ICMP events are masked by MSR[DE] = 0 when operating in internal debug mode.
35 IAC1C1 Instruction address compare 1 debug event count 1 enable.
0 Counting IAC1 debug events by counter 1 is disabled.
1 Counting IAC1 debug events by counter 1 is enabled.
36 IAC2C1 Instruction address compare2 debug event count 1 enable.
0 Counting IAC2 debug events by counter 1 is disabled.
1 Counting IAC2 debug events by counter 1 is enabled.
37 IAC3C1 Instruction address compare 3 debug event count 1 enable.
0 Counting IAC3 debug events by counter 1 is disabled.
1 Counting IAC3 debug events by counter 1 is enabled.
38 IAC4C1 Instruction address compare 4 debug event count 1 enable.
0 Counting IAC4 debug events by counter 1 is disabled.
1 Counting IAC4 debug events by counter 1 is enabled.
39 DAC1RC1 Data address compare 1 read debug event count 1 enable
0 Counting DAC1R debug events by counter 1 is disabled.
1 Counting DAC1R debug events by counter 1 is enabled.
40 DAC1WC1 Data address compare 1 write debug event count 1 enable
0 Counting DAC1W debug events by counter 1 is disabled.
1 Counting DAC1W debug events by counter 1 is enabled.
41 DAC2RC1 Data address compare 2 read debug event count 1 enable
0 Counting DAC2R debug events by counter 1 is disabled.
1 Counting DAC2R debug events by counter 1 is enabled.
42 DAC2WC1 Data address compare 2 write debug event count 1 enable
0 Counting DAC2W debug events by counter 1 is disabled.
1 Counting DAC2W debug events by counter 1 is enabled.
43 IRPTC1 Interrupt taken debug event count 1 enable.
0 Counting IRPT debug events by counter 1 is disabled.
1 Counting IRPT debug events by counter 1 is enabled.
44 RETC1 Return debug event count 1 enable.
0 Counting RET debug events by counter 1 is disabled.
1 Counting RET debug events by counter 1 is enabled.
45 DEVT1C2 External debug event 1 count 2 enable.
0 Counting DEVT1 debug events by counter 2 is disabled.
1 Counting DEVT1 debug events by counter 2 is enabled.
Freescale Semiconductor
Table 2-20. DBCR3 Field Descriptions
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
1
.
1
.
1
.
1
.
Register Model
2-45