Freescale Semiconductor e200z3 Reference Manual page 436

E–F
enabling, using, and exiting external debug mode,
9-32
entering debug mode, 9-23
register access requirements, 9-21–9-23
signals, 9-13
external, 9-14
internal, 9-14
overview
debug APU, 9-2
hardware debug facilities, 9-2
software debug facilities, 9-1
Book E compatibility, 9-2
power management considerations, 8-3
registers, 2-33–2-47, 9-4
control state register (CTL), 9-25
CPU status and control scan chain (CPUSCR), 9-24
instruction address FIFO buffer (PC FIFO), 9-29
instruction register (IR), 9-25
machine state register (MSR), 9-29
OnCE command register (OCMR), 9-17
OnCE control register (OCR), 9-20
OnCE status register (OSR), 9-17
program counter register (PC), 9-28
write-back bus (WBBR (lower and upper)), 9-28
software debug events and exceptions, 9-4
watchpoint signaling, 9-31
DEC (decrementer register), 2-32
DECAR (decrementer auto-reload register), 2-32
Decrementer
DEC (decrementer register), 2-32
DECAR (decrementer auto-reload register), 2-32
decrementer interrupt, 4-18
see also Interrupt handling
Doze mode, see Power management
DS (development status register), 10-14
DSI (data storage interrupt), 4-12
see also Interrupt handling
DSRR0 (debug save/restore register 0), 2-25, 4-1
DSRR1 (debug save/restore register 1), 2-25, 4-1
DTC (data trace control register), 10-19
DTEA1–2 (data trace end address 1, 2 registers), 10-20
DTSA1–2 (data trace start address 1, 2 reg's), 10-20
E
e200z6 overview, 1-1
auxiliary processing units (APUs)
machine check
rfmci instruction, 1-6
single-precision floating-point (SPFP)
instructions, 1-6
block diagram, 1-2
comparisons with legacy PowerPC devices, 1-13
Index-2
e200z3 Power Architecture Core Reference Manual, Rev. 2
exception handling, 1-14
instruction set compatibility, 1-13
little endian mode, 1-15
memory management unit (MMU) and TLBs, 1-14
reset operation, 1-15
exceptions and interrupt handling, 1-7
critical interrupts, 1-9
interrupt classes, 1-8
interrupt registers, 1-9
interrupt types, 1-8
features, 1-3
programming model
instruction set, 1-6
Effective address (EA), 5-4
translation to real address, see Memory management unit
(MMU)
Embedded floating-point instructions, 1-6
Embedded single-precision floating-point (SPFP) APUs
instructions, 3-2, 3-14–3-15
ESR (exception syndrome register), 2-22, 4-4
Exception handling
extended model, 1-7
overview, 1-14
Exceptions
definition, 4-1
enabling and disabling, 4-31
exception handling, see Interrupt handling
exception processing, 4-2
exception syndrome register (ESR), 2-22, 4-4
priorities, 4-28
recognition and priority, 4-27
register settings
ESR, 4-1
MSR, 4-5
returning from an exception handler, 4-32
summary table, 4-3
terminology, 4-2
types (more granular than interrupts)
alignment exception, 4-15
data access exceptions, 5-14
debug exceptions, 4-22
DSI exception, 4-12, 4-20, 4-21
exceptions and conditions, 4-3
FP unavailable exception, 4-17
machine check exception, 4-11
program exception, 4-16
reset exception, 4-24
system call exception, 4-17
TLB miss exceptions, 5-8
F
Fixed-interval timer
Index
Freescale Semiconductor