Freescale Semiconductor e200z3 Reference Manual page 317

Figure 7-20 shows functional timing for a burst write transfer. The second burst is only one beat long.
m_clk
p_htrans
p_addr,p_hprot
p_hsize,
p_hbstrb, etc
p_hburst
p_hunalign
p_hwrite
p_hrdata
p_hwdata
p_hready
p_hresp
This same scenario can occur for read bursts as well.
7.5.3 Address Retraction
Address retraction is the process of replacing a request with a new unrelated one. Although the AMBA
AHB protocol requires an access request to remain driven unchanged once presented on the bus, higher
system performance may be obtained if this aspect of the protocol is modified to allow an access request
to be changed before being taken.
operation. Signal p_[d,i]_hready for the first request (addr
inserted during C3 until p_[d,i]_hready is recognized.
Meanwhile, a subsequent request has been generated by the CPU for addr
the previous transaction is still outstanding. The address and transfer attributes are retracted in cycle C3,
and a new access request to addr
is completing. Data for addr
a request for addr is made. The request for access to addr
w
and a ready/OKAY response is provided by the slave device. In cycle C5, no further accesses are requested.
Freescale Semiconductor
1 2
nonseq seq
addr x addr x+8
data x
okay okay
Figure 7-20. Burst Write Transfers, Single-Beat burst
Figure 7-27 shows an example of address retraction during wait state
is requested and are taken at the end of C3 because the previous access
z
and a ready/OKAY response is driven back by the slave device. In cycle C4,
x
e200z3 Power Architecture Core Reference Manual, Rev. 2
Burst Write
3 4
seq nonseq
addr x+16 addr y
incr
data x+8 data x+16
okay okay
) is not asserted during C2, so a wait state is
x
which is not taken in C2 since
y
is taken at the end of C4; during C5, the data
w
External Core Complex Interfaces
5 6
idle
data y
okay
7-49