Freescale Semiconductor e200z3 Reference Manual page 212

Interrupts and Exceptions
Register
MSR UCLE 0
SPE 0
WE
CE
EE
4
DBSR Unconditional debug event:
Instruction complete debug event:
Branch taken debug event:
Interrupt taken debug event:
Critical interrupt taken debug event:
Trap instruction debug event:
Instruction address compare:
Data address compare:
Return debug event:
Critical return debug event:
Debug counter event:
External debug event:
(optional) Imprecise debug event flag
ESR Unchanged
MCSR Unchanged
4-24
Table 4-25. Debug Interrupt Register Settings (continued)
0
2
—/0
2
—/0
e200z3 Power Architecture Core Reference Manual, Rev. 2
Setting Description
PR 0
FP 0
ME —
FE0 0
UDE
ICMP
BRT
IRPT
CIRPT
TRAP
{IAC1, IAC2, IAC3, IAC4}
{DAC1R, DAC1W, DAC2R, DAC2W}
RET
CRET
{DCNT1, DCNT2}
{DEVT1, DEVT2}
{IDE}
DE 0
FE1 0
IS 0
DS 0
2,3
RI —/0
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