Freescale Semiconductor e200z3 Reference Manual page 257

Mnemonic
lbzux, e_lha
lbzx, e_lhau
lha, e_lhz
lhau, e_lhzu
lhaux
lhax
lhbrx
lhz, se_lhz
lhzu
lhzux
lhzx
lmw, e_lmw
lwarx
lwbrx
lwz, e_lwz, se_lwz
lwzu, e_lwzu
lwzux
lwzx
mbar
mcrf, e_mcrf
mcrxr
mfcr
mfmsr
mfspr (except, debug, MMU), se_mfctr, se_mflr
mfspr, (debug, MMU)
msync
mtcrf
mtmsr
mtspr, (debug, MMU), se_mtctr, se_mtlr
mtspr, (except, debug, MMU)
mulhwu[.]
mulhw[.]
mulli, e_mulli, e_mull2i
Freescale Semiconductor
Table 6-3. Instruction Timing by Mnemonic (continued)
e200z3 Power Architecture Core Reference Manual, Rev. 2
Instruction Pipeline and Execution Timing
Latency Serialization
1 None Aligned
1 None Aligned
1 None Aligned
1 None Aligned
1 None Aligned
1 None Aligned
1 None Aligned
1 None Aligned
1 None Aligned
1 None Aligned
1 None Aligned
1 +(n/2) None
1 None
1 None Aligned
1 None Aligned
1 None Aligned
1 None Aligned
1 None Aligned
1 Completion Plus additional synchronization time
1 None
1 Completion
1 None
1 None
1 None
3 Completion Plus additional synchronization time
1 Completion Plus additional synchronization time
2 None
2 Completion Plus additional synchronization time
2 Completion Plus additional synchronization time
1 None
1 None
1 None
1 None
Comments
6-19