Freescale Semiconductor e200z3 Reference Manual page 354

Debug Support
Table 9-8. OnCE Control Register Bit Definitions (continued)
Bits Name
16 D_DMDIS Data side debug MMU disable control bit. Controls whether the MMU is enabled normally or is disabled
during a debug session for data accesses.
0 MMU not disabled for debug sessions. The MMU functions normally
1 MMU disabled for debug sessions. For data accesses, no address translation is performed (1:1 address
mapping) and the TLB WIMGE bits are taken from the OCR bits D_DW, D_DI, D_DM, D_DG, and D_DE
bits. The SR, SW, UR, and UW access permission control bits are set to allow full access. When disabled,
no TLB miss or TLB exceptions are generated for data accesses. External access errors can still occur.
17–18 — Reserved, should be cleared.
19 D_DW Data side debug TLB W attribute bit. Provides the W attribute bit for data accesses when the MMU is
disabled for data accesses during a debug session.
20 D_DI Data side debug TLB I attribute bit. Provides the I attribute bit for data accesses when the MMU is disabled
for data accesses during a debug session.
21 D_DM Data side debug TLB M attribute bit. Provides the M attribute bit for data accesses when the MMU is disabled
for data accesses during a debug session.
22 D_DG Data side debug TLB G attribute bit. Provides the G attribute bit for data accesses when the MMU is disabled
for data accesses during a debug session.
23 D_DE Data side debug TLB E attribute bit. Provides the E attribute bit for data accesses when the MMU is disabled
for data accesses during a debug session.
24–28 — Reserved, should be cleared.
Wakeup request bit. Used to force the p_wakeup output to be asserted. To ensure that debug resources
29 WKUP
may be properly accessed by external hardware through scan sequences, debug firmware can use this
control function to request that the chip-level clock controller restore the m_clk input to normal operation
regardless of whether the core is in a low-power state.
30 FDB Force breakpoint debug mode. Determines whether the processor is operating in breakpoint debug enable
mode. The processor may be placed in breakpoint debug enable mode by setting this bit. In breakpoint
debug enable mode, execution of the bkpt pseudo-instruction causes the processor to enter debug mode,
as if the jd_de_b input had been asserted. FDB is qualified with DBCR0[EDM], which must be set for FDB
to take effect.
31 DR CPU debug request control. Used to unconditionally request the CPU to enter debug mode. The CPU
indicates that debug mode has been entered via the data scanned out in the shift-IR state.
0 No debug mode request
1 Unconditional debug mode request. The processor enters debug mode at the next instruction boundary.
9.5.6 Access to Debug Resources
Resources contained in the OnCE module that do not require the core to be halted for access may be
accessed without interfering with processor execution. Accesses to other resources such as the CPUSCR
require the core to be placed in debug mode to avoid synchronization hazards. Debug firmware may ensure
that it is safe to access these resources by determining the state of the core before access.
A scan operation to update the CPUSCR is required before exiting debug
mode.
9-22
NOTE
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Freescale Semiconductor