Freescale Semiconductor e200z3 Reference Manual page 95

Bits Name
60 DAC1RT1 Data address compare 1 read trigger counter 1 enable.
0 No effect.
1 A DAC1R debug event triggers counter 1 operation.
61 DAC1WT1 Data address compare 1 write trigger counter 1 enable.
0 No effect.
1 A DAC1W debug event triggers counter 1 operation.
62 CNT2T1 Debug counter 2 trigger counter 1 enable.
0 No effect.
1 Counter 2 decrementing to 0 triggers counter 1 operation.
63 CONFIG Debug counter configuration.
0 Counter 1 and counter 2 are independent counters.
1 Counter 1 and counter 2 are concatenated into a single 32-bit counter. The event count
1
If the DACx field in DBCR0 is set to restrict events to only reads or only writes, only those events are counted
if enabled in DBCR3. In general, DAC events should be disabled in DBCR0.
Perform updates to DBCR0, DBSR, DBCR3, and DBCNT carefully if the
counters are enabled for counting ICMP events. An instruction that updates
the counters or control over the counters can cause one or more counter
events (DCNT1, DCNT2, CNT1TRG), even if the result of the instruction
is to modify the counter value or control value to a state where counter
events are not expected. This is due to the pipelined nature of the counter
and control operation.
• For DBCNT, if a counter is enabled to count ICMP events,
MSR[DE] = 1, and the counter value is 1 before execution of an mtspr
that loads the counter with a different value, a counter event is generated
after the mtspr completes, even though the counter is loaded with a new
value. When the mtspr finishes executing, a debug event is posted, but
the counter holds the newly written value. The new counter value is
assigned at the completion of an mtspr that modifies a counter,
regardless of whether a debug event is generated based on the old
counter value. To avoid this, modify DBCNT and DBCR3 only when
there is no possibility of a counter-related debug event on the mtspr.
• For DBCR3, if a counter is enabled to count ICMP events,
MSR[DE] = 1, and the counter value is 1 before execution of an mtspr
that is loading DBCR3 with a different value, a counter event may be
generated after the mtspr completes, even though DBCR3 is loaded
with a value that prevents the particular event from being counted.
When the mtspr finishes executing, a debug event is posted, but the
Freescale Semiconductor
Table 2-20. DBCR3 Field Descriptions (continued)
control bits for counter 1 are used and the event count control bits for counter 2 are
ignored.
NOTE
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
Register Model
2-47