Freescale Semiconductor e200z3 Reference Manual page 275

Signal Name I/O Reset
j_shift_ir O
j_capture_dr O
j_shift_dr O
j_update_gp_reg O
j_rti O
j_key_in I
j_en_once_regsel
O
j_nexus_regsel
O
j_lsrl_regsel
O
j_gp_regsel[0:11] O
j_id_sequence[0:1] I
j_id_version[0:3] I
j_serial_data I
7.3 Signal Descriptions
Table 7-2 describes the processor clock, m_clk.
Signal I/O
m_clk
I Processor clock. The synchronous clock source for the core. Because the core is designed for static
operation, m_clk can be gated off to lower power dissipation (for example, during low-power stopped
states).
Table 7-3 describes signals that are related to reset. The core supports several reset input signals for the
CPU and JTAG/OnCE control logic: m_por, p_reset_b, and j_trst_b. The reset domains are partitioned
such that the CPU p_reset_b signal does not affect JTAG/OnCE logic and j_trst_b does not affect
processor logic. It is possible and desirable to access OnCE registers while the processor is running or in
reset. It is also possible and desirable to assert j_trst_b and clear the JTAG/OnCE logic without affecting
the processor state.
The synchronization logic between the processor and debug module requires an assertion of either j_trst_b
or m_por during initial processor power-on reset to ensure proper operation. If the pin associated with
j_trst_b is designed with a pull-up resistor and left floating, assertion of m_por is required during the initial
power-on processor reset. Similarly, for those systems that do not have a power-on reset circuit and choose
to tie m_por low, it is required to assert j_trst_b during processor power-up reset. When a power-up reset
is achieved, the two resets can be asserted independently.
A reset output signal, p_resetout_b, is also provided.
Freescale Semiconductor
Table 7-1. Interface Signal Definitions (continued)
0 Shift_IR state of JTAG controller
0 Parallel test data register load state of JTAG controller
0 TAP controller in shift DR state
0 Updates JTAG controller test data register
0 JTAG controller run-test-idle state
Input for providing data to be shifted out during shift_IR state when jd_en_once is
negated
0 External enable OnCE register select
0 External Nexus register select
0 External LSRL register select
0 General-purpose external JTAG register select
JTAG ID register (2 msbs of sequence field)
JTAG ID register version field
Serial data from external JTAG registers
Table 7-2. Processor Clock Signal Description
Signal Description
e200z3 Power Architecture Core Reference Manual, Rev. 2
External Core Complex Interfaces
Definition
7-7