Freescale Semiconductor e200z3 Reference Manual page 277

Table 7-4. Descriptions of Signals for the Address and Data Buses
Signal I/O
p_[d,i]_haddr[31:0] O Address bus. Provides the address for a bus transfer. According to the AHB definition,
p_[d,i]_haddr[31] is the msb and p_[d,i]_haddr[0] is the lsb.
p_[d,i]_hrdata[63:0 I Read data bus. Provides data to the core on read transfers. The read data bus can transfer 8, 16, 24,
] 32, or 64 bits per transfer. According to the AHB definition, p_[d,i]_hrdata63 is the msb and
p_[d,i]_hrdata0 is the lsb.
p_d_hwdata[63:0] O Write data bus. Transfers data from the core on write transfers. The write data bus can transfer 8, 16,
24, 32, or 64 bits of data per bus transfer. According to the AHB definition, p_d_hwdata[63] is the msb
and p_d_hwdata[0] is the lsb.
Table 7-5 describes transfer attribute signals, which provide additional information about the bus transfer
cycle. Attributes are driven with the address at the start of a transfer.
Signal I/O
p_[d,i]_htrans[1:0] O Transfer type. The processor drives p_[d,i]_htrans[1:0] to indicate the current transfer type as follows:
00 IDLE—No data transfer is required. Slaves must terminate IDLE transfers with a zero wait-state
01 BUSY—(The core does not use the BUSY encoding and does not present this type of transfer to
10 NONSEQ—Indicates the first transfer of a burst, or a single transfer. Address and control signals
11 SEQ—Indicates the continuation of a burst. Address and control signals are related to the previous
If the p_[d,i]_htrans[1:0] encoding is not IDLE or BUSY, a transfer is being requested.
p_[d,i]_hwrite O Write. Defines the data transfer direction for the current bus cycle.
Meaning
Freescale Semiconductor
Memory Byte AddressWired to p_[d,i]_hrdata Bits
0007:0
00115:8
01023:16
01131:24
10039:32
10147:40
11055:48
11163:56
Memory Byte AddressWired to p_d_hwdata Bits
0007:0
00115:8
01023:16
01131:24
10039:32
10147:40
11055:48
11163:56
Table 7-5. Descriptions of Transfer Attribute Signals
OKAY response and ignore the (non-existent) transfer.
a bus slave.) Master is busy; burst transfer continues.
are unrelated to the previous transfer.
transfer. Control signals are the same. Address was incremented by the size of the data transferred
(optionally wrapped).
State Asserted—The current bus cycle is a write.
Negated—The current bus cycle is a read.
e200z3 Power Architecture Core Reference Manual, Rev. 2
External Core Complex Interfaces
Signal Description
Signal Description
7-9