Freescale Semiconductor e200z3 Reference Manual page 162

Power architecture core
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Instruction Model
Opcode
Format
Extended
Primary
(Inst
(Inst
)
21:31
0:5
X
011111
01100 11100 0
X
011111
01100 11100 1
X
011111
01101 10111 /
X
011111
01101 11100 0
X
011111
01101 11100 1
XFX
011111
01110 00011 /
X
011111
01110 01011 0
X
011111
01110 01011 1
XFX
011111
01110 10011 /
X
011111
01110 10110 /
X
011111
01110 11100 0
X
011111
01110 11100 1
X
011111
01111 01011 0
X
011111
01111 01011 1
X
011111
10000 00000 /
X
011111
10000 01000 0
X
011111
10000 01000 1
X
011111
10000 01010 0
X
011111
10000 01010 1
X
011111
10000 10101 /
X
011111
10000 10110 /
X
011111
10000 10111 /
X
011111
10000 11000 0
X
011111
10000 11000 1
X
011111
10001 01000 0
X
011111
10001 01000 1
X
011111
10001 10110 /
X
011111
10001 10111 /
Legend:
- Don't care, usually part of an operand field
/ Reserved bit, invalid instruction form if encoded as 1
? Allocated for implementation-dependent use. See User' Manual for the implementation
3-34
Table 3-12. Instructions Sorted by Opcode (continued)
Mnemonic
)
orc
OR with Complement
orc.
OR with Complement and record CR
sthux
Store Halfword with Update Indexed
or
OR
or.
OR and record CR
mtdcr
Move To Device Control Register
divwu
Divide Word Unsigned
divwu.
Divide Word Unsigned and record CR
mtspr
Move To Special Purpose Register
dcbi
Data Cache Block Invalidate
nand
NAND
nand.
NAND and record CR
divw
Divide Word
divw.
Divide Word and record CR
mcrxr
Move to Condition Register from XER
subfco
Subtract From Carrying and record OV
subfco.
Subtract From Carrying and record OV and CR
addco
Add Carrying and record OV
addco.
Add Carrying and record OV and CR
lswx
Load String Word Indexed
lwbrx
Load Word Byte-Reverse Indexed
lfsx
Load Floating-Point Single Indexed
srw
Shift Right Word
srw.
Shift Right Word and record CR
subfo
Subtract From and record OV
subfo.
Subtract From and record OV and CR
tlbsync
TLB Synchronize
lfsux
Load Floating-Point Single with Update Indexed
e200z3 Power Architecture Core Reference Manual, Rev. 2
Instruction
Freescale Semiconductor

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