Freescale Semiconductor e200z3 Reference Manual page 335

Debug Support
When hardware debug is enabled (DBCR0[EDM] = 1), the registers and resources described in
Section 9.3, "Debug Registers," are reserved for use by the external debugger. The events described in
Section 9.3, "Debug Registers," are also used for external debugging, but exceptions are not generated to
running software. Debug events enabled in the respective DBCR0–DBCR3 registers are recorded in the
DBSR regardless of MSR[DE], and no debug interrupts are generated unless the resource is granted back
to software via DBERC0 settings. Instead, the CPU enters debug mode when an enabled event causes a
DBSR bit to become set. DBCR0[EDM] may only be written through the OnCE port.
A program trace program counter FIFO (PC FIFO) is also provided to support program change-of-flow
capture.
To perform write accesses from the external hardware debugger, most debug resources (registers) require
the CPU clock (m_clk) to be running.
9.2.4 Sharing Debug Resources by Software/Hardware in e200z335
Debug resources may be shared by a hardware debugger and software debug based on the settings of
debug control register DBERC0. When DBCR0[EDM] is set, DBERC0 settings determine which debug
resources are allocated to software and which resources remain under exclusive hardware control.
Software-owned DBSR bits being set will cause a debug interrupt to occur when enabled with MSR[DE]
and DBCR0[IDM]=1. Hardware-owned DBSR bits will cause an entry into debug mode if set. DBERC0
is read-only by software. When resource sharing is enabled, (DBCR0[EDM]=1 and DBERC0[IDM]=1),
only software-owned resources may be modified by software, and all status bits associated with
hardware-owned resources will be forced to 0 in DBSR when read by software via a mfspr instruction.
Hardware always has full access to all registers and all register fields through the OnCE register access
mechanism, and it is up to the debug firmware to properly implement modifications to these registers
with read-modify-write operations to implement any control sharing with software. Settings in DBERC0
should be considered by the debug firmware in order to preserve software settings of control and status
registers as appropriate when hardware modifications to the debug registers is performed.
9.2.4.1 Simultaneous Hardware and Software Debug Event Handing in
e200z335
Since it is possible that a hardware "owned" resource can produce a debug event in conjunction with a
software-owned resource producing a different debug event simultaneously, a priority ordering
mechanism is implemented which guarantees that the hardware event is handled as soon as possible, while
preserving the recognition of the software event. The CPU will give highest priority to the software event
initially in order to reach a recoverable boundary, and then will give highest priority to the hardware event
in order to enter debug mode as near the point of event occurrence as possible. This is implemented by
allowing software exception handing to begin internal to the CPU and to reach the point where the current
program counter and MSR values have been saved into DSRR0/1, and the new PC pointing to the debug
interrupt handler, along with the new MSR updates. At this point, hardware priority takes over, and the
CPU enters debug mode.
Figure 9-1 shows the core debug resources.
e200z3 Power Architecture Core Reference Manual, Rev. 2
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