Parallel Signature Control Register (Pscr) - Freescale Semiconductor e200z3 Reference Manual

D31 (D63) D30 (D62) D29 (D61) D28 (D60)
d q d q
+ +
The parallel signature unit consists of seven registers as described in this section. Access to these registers
is privileged. No user-mode access is allowed.
Proper access of the PSU registers requires an mfdcr that reads a PSU
register to be proceeded by either mbar or msync. To ensure that the effects
of an mtdcr to one of the PSU registers takes effect, the mtdcr is followed
by a context synchronizing instruction (sc, isync, rfi, rfci, rfdi).
2.19.1

Parallel Signature Control Register (PSCR)

PSCR, shown in Figure
32
Field
Reset
R/W
DCR
Freescale Semiconductor
Data Bus (p_d_hrdata, p_d_hwdata)
d q d q
...
+ +
PSHR, (PSLR)
2-55, controls operation of the parallel signature unit.
—
Figure 2-55. Parallel Signature Control Register (PSCR)
e200z3 Power Architecture Core Reference Manual, Rev. 2
D22 (D54) D21 (D53) D20 (D52)
d q d q d q
+ + +
NOTE
57 58 59 60
CNTEN —
All zeros
R/W
DCR 272
Register Model
D1 (D33) D0 (D32)
d q d q
...
+ +
61 62 63
RDEN WREN INIT
2-77