Freescale Semiconductor e200z3 Reference Manual page 5

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2.9.4.3 Machine Check Syndrome Register (MCSR)........................................................ 2-26
2.10 Software-Use SPRs (SPRG0-SPRG7 and USPRG0) ................................................... 2-27
2.11 Timer Registers .............................................................................................................. 2-28
2.11.1 Timer Control Register (TCR)................................................................................... 2-29
2.11.2 Timer Status Register (TSR)...................................................................................... 2-30
2.11.3 Time Base (TBU and TBL) ....................................................................................... 2-31
2.11.4 Decrementer Register ................................................................................................ 2-33
2.11.5 Decrementer Auto-Reload Register (DECAR).......................................................... 2-33
2.12 Debug Registers ............................................................................................................. 2-34
2.12.1 Debug Address and Value Registers.......................................................................... 2-34
2.12.1.1 Instruction Address Compare Registers (IAC1-IAC4) ......................................... 2-34
2.12.1.2 Data Address Compare Registers (DAC1-DAC2)................................................ 2-35
2.12.1.3 Data Value Compare Registers (DVC1-DVC2) (e200z335 only) ........................ 2-35
2.12.2 Debug Counter Register (DBCNT) ........................................................................... 2-36
2.12.3 Debug Control and Status Registers (DBCR0-DBCR3)........................................... 2-36
2.12.3.1 Debug Control Register 0 (DBCR0)...................................................................... 2-36
2.12.3.2 Debug Control Register 1 (DBCR1)...................................................................... 2-39
2.12.3.3 Debug Control Register 2 (DBCR2)...................................................................... 2-41
2.12.3.4 Debug Control Register 3 (DBCR3)...................................................................... 2-43
2.12.3.5 Debug Control Register 4 (DBCR4) (e200z335 only) .......................................... 2-48
2.12.4 Debug Status Register (DBSR).................................................................................. 2-49
2.12.5 Debug External Resource Control Register (DBERC0)............................................ 2-50
2.13 Hardware Implementation-Dependent Registers........................................................... 2-57
2.13.1 Hardware Implementation-Dependent Register 0 (HID0)......................................... 2-57
2.13.2 Hardware Implementation-Dependent Register 1 (HID1)......................................... 2-59
2.14 Branch Target Buffer (BTB) Registers .......................................................................... 2-61
2.14.1 Branch Unit Control and Status Register (BUCSR) .................................................. 2-61
2.15 L1 Cache Configuration Registers................................................................................. 2-61
2.15.1 L1 Cache Configuration Register 0 (L1CFG0) ......................................................... 2-61
2.16 MMU Registers.............................................................................................................. 2-62
2.16.1 MMU Control and Status Register 0 (MMUCSR0) .................................................. 2-62
2.16.2 MMU Configuration Register (MMUCFG) .............................................................. 2-62
2.16.3 TLB Configuration Registers (TLBnCFG)................................................................ 2-63
2.16.3.1 TLB Configuration Register 0 (TLB0CFG) .......................................................... 2-63
2.16.3.2 TLB Configuration Register 1 (TLB1CFG) .......................................................... 2-64
2.16.4 MMU Assist Registers (MAS0-MAS4, MAS6) ....................................................... 2-65
2.16.5 Process ID Register (PID0)........................................................................................ 2-69
2.17 Support for Fast Context Switching............................................................................... 2-69
2.17.1 Context Control Register (CTXCR) .......................................................................... 2-70
2.18 SPR Register Access...................................................................................................... 2-70
2.18.1 Invalid SPR References ............................................................................................. 2-70
Freescale Semiconductor
Contents
Title
e200z3 Power Architecture Core Reference Manual, Rev. 2
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Number
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