Exception Syndrome Register (Esr) - Freescale Semiconductor e200z3 Reference Manual

SPR numbers corresponding to IVOR16–IVOR31 are reserved. IVOR32–IVOR47 and IVOR60–IVOR63
are reserved. SPR numbers for IVOR32–IVOR63 are allocated for implementation-dependent use
(IVOR32–IVOR34 (SPR 528–530) are defined by the EIS). IVOR assignments are shown in
IVOR Number SPR
IVOR0 400 Critical input
IVOR1 401 Machine check
IVOR2 402 Data storage
IVOR3 403 Instruction storage
IVOR4 404 External input
IVOR5 405 Alignment
IVOR6 406 Program
IVOR7 407 Floating-point unavailable
IVOR8 408 System call
IVOR9 409 Auxiliary processor unavailable. (Defined by the EIS but not supported in the e200z3.)
IVOR10 410 Decrementer
IVOR11 411 Fixed-interval timer interrupt
IVOR12 412 Watchdog timer interrupt
IVOR13 413 Data TLB error
IVOR14 414 Instruction TLB error
IVOR15 415 Debug
IVOR16–IVOR31 —
IVOR32 528 SPE APU unavailable (EIS–defined)
IVOR33 529 SPE floating-point data exception (EIS–defined)
IVOR34 530 SPE floating-point round exception (EIS–defined)
IVOR35–IVOR63 —
2.9

Exception Syndrome Register (ESR)

The ESR, shown in Figure
interrupt type. The e200z3 adds implementation-specific bits to this register.
Freescale Semiconductor
Table 2-12. IVOR Assignments
Reserved for future architectural use
Allocated for implementation-dependent use
2-18, provides a syndrome to distinguish exceptions that can generate the same
e200z3 Power Architecture Core Reference Manual, Rev. 2
Interrupt Type
Register Model
Table 2-12.
2-23