Freescale Semiconductor e200z3 Reference Manual page 223

Chapter 5
Memory Management Unit
This chapter describes the implementation details of the e200z3 core complex MMU relative to the Book E
architecture and the Freescale Book E standards.
5.1 Overview
The e200z3 memory management unit is a 32-bit PowerPC Book E–compliant implementation.
5.1.1 MMU Features
The MMU of the e200z3 core has the following feature set:
• Freescale Book E implementation standard (EIS) MMU architecture compliant
• 32-bit effective address translated to 32-bit real address (using a 41-bit interim virtual address)
• 16-entry, fully associative, translation lookaside buffer (TLB1) that supports the nine page sizes
(4 Kbytes, 16 Kbytes, 64 Kbytes, 256 Kbytes, 1 Mbyte, 4 Mbytes, 16 Mbytes, 64 Mbytes,
256 Mbytes), shown in
• One 32-bit PID register (PID0) for supporting up to 255 translation IDs at any time in the TLB
• No page table format defined; software is free to use its own page table format
• Hardware assist for TLB miss exceptions
• TLB1 managed by tlbre, tlbwe, tlbsx, tlbsync, and tlbivax instructions and six MMU assist
(MAS) registers
• IPROT bit implemented in TLB1 prevents invalidations, protecting critical entries (so designated
by having the IPROT bit set) from being invalidated.
5.1.2 TLB Entry Maintenance Features Summary
The TLB entries of the e200z3 core complex must be loaded and maintained by the system software; this
includes performing any required table search operations in memory. The e200z3 provides support for
maintaining TLB entries in software with the resources shown in
features are defined at the Freescale Book E level.
Freescale Semiconductor
Table 5-2
e200z3 Power Architecture Core Reference Manual, Rev. 2
Table 5-1. Note that many of these
5-1