Freescale Semiconductor e200z3 Reference Manual page 320

External Core Complex Interfaces
Figure 7-23 shows an example of error termination.
m_clk
p_htrans
p_addr,p_hprot
p_hsize ,
p_hbstrb , etc
p_hburst
p_hunalign
p_hwrite
p_hrdata
p_hwdata
p_hready
p_hresp
Figure 7-23. Read and Write Transfers: Instruction Read with Error, Data Read, Write,
The first read request (addr
prefetch.
The second read request (addr
(no p_[d,i]_hready assertion). An error response is signaled by the addressed slave for addr
ERROR onto the p_[d,i]_hresp[2:0] inputs. This is the first cycle of the two cycle error response protocol.
p_[d,i]_hready is asserted during C3 for the first read access (addr
driven on p_[d,i]_hresp[2:0], terminating the access. The read data bus is undefined.
In this example of error termination, the CPU continues to request an access to addr
of C3. During C4, read data is supplied for the addr
Also during C4, a request is generated for a write to addr
second access is terminating.
Data for the addr write cycle is driven in C5, the cycle after the access is taken.
z
During C5, a ready/OKAY response is signaled to complete the write cycle to addr
In this example of error termination, a subsequent access remained requested. This does not always occur
when certain types of transfers are terminated with error. The following figures outline cases where an
error termination for a given cycle causes a pending request to be aborted prior to initiation.
7-52
1 2
nonseq nonseq
addr x addr y
single single
okay error
Full Pipelining
) is taken at the end of cycle C1 because the bus is idle. It is an instruction
x
) is not taken at the end of C2 because the first access is still outstanding
y
y
e200z3 Power Architecture Core Reference Manual, Rev. 2
3 4
nonseq
addr z
single
data x data y
error okay
) while the ERROR encoding remains
x
read, and the access is terminated normally during C4.
, which is taken at the end of C4 because the
z
5 6
idle
data z
okay
by driving
x
. It is taken at the end
y
.
z
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