Freescale Semiconductor e200z3 Reference Manual page 348

Debug Support
Table 9-5 describes the OnCE interface signals.
Signal Name I/O
OnCE enable I
( jd_en_once)
OnCE debug request I/O
( jd_de_b) /event
(jd_de_en )
OnCE debug output O
(jd_debug_b)
9-16
Table 9-5. OnCE Interface Signals
The OnCE enable signal, jd_en_once, is used to enable the OnCE controller to allow certain
instructions and operations to be executed. Assertion of this signal enables the full OnCE
command set, as well as operation of control signals and OnCE control register functions.
When this signal is disabled, only the Bypass, ID and Enable_OnCE commands are executed
by the OnCE unit, and all other commands default to the Bypass command. The OSR is not
visible when OnCE operation is disabled. Also OCR functions are also disabled, as is the
operation of the jd_de_b input. Secure systems may choose to leave jd_en_once negated until
a security check has been performed. Other systems should tie this signal asserted to enable
full OnCE operation. The j_en_once_regsel output signal is provided to assist external logic
performing security checks. Refer to
description of the j_en_once_regsel output.
The jd_en_once input must change state only during the test-logic-reset, Run-Test/Idle, or
Update-DR TAP states. A new value takes effect after one additional j_tclk cycle of
synchronization. In addition, jd_enable_once must not change state during a debug session, or
undefined activity may occur.
The system-level bidirectional open drain debug event pin, DE_b , (not part of the interface
described in Chapter 7, "External Core Complex
the debug mode of operation from an external command controller (when input) as well as a
fast means of acknowledging entry into debug mode of operation to an external command
controller (when output). The assertion of this pin by a command controller causes the CPU
core to finish the current instruction being executed, save the instruction pipeline information,
enter debug mode, and wait for commands to be entered. If DE_b was used to enter debug
mode, DE_b must be negated after the OnCE controller responds with an acknowledge and
before sending the first OnCE command. The assertion of this pin by the CPU core
acknowledges that it has entered the debug mode and is waiting for commands to be entered.
To support operation of this system pin, the OnCE logic supplies the jd_de_en output and
samples the jd_de_b input when OnCE is enabled ( jd_en_once set). Assertion of jd_de_b
causes the OnCE logic to place the CPU into debug mode. Once debug mode has been
entered, the jd_de_en output is asserted for three j_tclk periods to signal an acknowledge;
jd_de_en can be used to enable the open-drain pulldown of the system level DE_b pin.
The OnCE debug output jd_debug_b is used to indicate to on-chip resources that a debug
session is in progress. Peripherals and other units may use this signal to modify normal
operation for the duration of a debug session, which may involve the CPU executing a sequence
of instructions solely for the purpose of visibility/system control that are not part of the normal
instruction stream the CPU would have executed had it not been placed in debug mode. This
signal is set the first time the CPU enters the debug state, and remains set until the CPU is
released by a write to the core OnCE command register (OCMD) with the GO and EX bits set,
and a register specified as either no register selected or the CPUSCR. This signal remains set
even though the CPU may enter and exit the debug state for each instruction executed under
control of the OnCE controller. See
more information on the function of the GO and EX bits. This signal is not normally used by the
CPU.
e200z3 Power Architecture Core Reference Manual, Rev. 2
1
Description
Section 9.5.5.3, "OnCE Control Register
Interfaces") provides a fast means of entering
Section 9.5.5.2, "OnCE Command Register
(OCR)," for a
(OCMD)," for
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