Freescale Semiconductor e200z3 Reference Manual page 387

Bits
7
6
5–4
3
2–0
10.4.10 Data Trace Start Address 1 and 2 Registers (DTSA1 and DTSA2)
The data trace start address registers, shown in
channel.
31
Field
Reset
R/W
Number
Figure 10-13. Data Trace Start Address Registers 1 and 2 (DTSA n )
10.4.11 Data Trace End Address Registers 1 and 2 (DTEA1 and DTEA2)
The data trace end address registers, shown in
channel.
31
Field
Reset
R/W
Number
Figure 10-14. Data Trace End Address Registers 1 and 2 (DTEA n )
Table 10-19 shows the range that is selected for data trace for various cases of DTSA being less than,
greater than, or equal to DTEA.
Freescale Semiconductor
Table 10-18. DTC Field Descriptions (continued)
Name
RC1 Range control 1
0 Condition trace on address within range
1 Condition trace on address outside of range
RC2 Range control 2
0 Condition trace on address within range
1 Condition trace on address outside of range
— Reserved, should be cleared.
DI1 Data access/instruction access trace 1
0 Condition trace on data accesses
1 Condition trace on instruction accesses
— Reserved, should be cleared.
Figure
Data Trace Start Address
DTSA1: 0xE; DTSA2: 0xF
Figure
DTEA1: 0x12; DTEA2: 0x13
e200z3 Power Architecture Core Reference Manual, Rev. 2
Description
10-13, define the start addresses for each trace
All zeros
Read/Write
10-14, define the end addresses for each trace
Data Trace End Address
All zeros
Read/Write
Nexus3/Nexus2+ Module
0
0
10-21