Freescale Semiconductor e200z3 Reference Manual page 267

Instruction Latency Throughput
efsabs
efsadd
efscfsf
efscfsi
efscfuf
efscfui
efscmpeq
efscmpgt
efscmplt
efsctsf
efsctsi
efsctsiz
efsctuf
efsctui
efsctuiz
efsdiv
efsdiv
efsmadd
efsmsub
efsmul
efsnabs
efsneg
efsnmadd
efsnmsub
efssub
efststeq
efststgt
efststlt
6.8 Operand Placement on Performance
The placement (location and alignment) of operands in memory affects relative performance of memory
accesses, and in some cases, affects it significantly.
Freescale Semiconductor
Table 6-8. Scalar SPE Floating-Point Instruction Timing
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
12 12 Blocking, no execution overlap with next instruction
12 12 Blocking, no execution overlap with next instruction
1 1 Destination also used as source
1 1 Destination also used as source
1 1
1 1
1 1
1 1 Destination also used as source
1 1 Destination also used as source
1 1
1 1
1 1
1 1
e200z3 Power Architecture Core Reference Manual, Rev. 2
Instruction Pipeline and Execution Timing
Comments
Table 6-9 indicates the effects for the e200z3 core.
6-29