Freescale Semiconductor e200z3 Reference Manual page 154

Power architecture core
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Instruction Model
Opcode
Format
Primary
Extended
(Inst
)
(Inst
0:5
21:31
X
011111
01100 11100 1
D
011000
––––– ––––– –
D
011001
––––– ––––– –
XL
010011
00001 10011 /
XL
010011
00001 00111 /
XL
010011
00001 10010 /
M
010100
––––– ––––– 0
M
010100
––––– ––––– 1
M
010101
––––– ––––– 0
M
010101
––––– ––––– 1
M
010111
––––– ––––– 0
M
010111
––––– ––––– 1
SC
010001
/ / / / / / / / /1 /
X
011111
00000 11000 0
X
011111
00000 11000 1
X
011111
11000 11000 0
X
011111
11000 11000 1
X
011111
11001 11000 0
X
011111
11001 11000 1
X
011111
10000 11000 0
X
011111
10000 11000 1
D
100110
––––– ––––– –
D
100111
––––– ––––– –
X
011111
00111 10111 /
X
011111
00110 10111 /
D
110110
––––– ––––– –
D
110111
––––– ––––– –
X
011111
10111 10111 /
Legend:
- Don't care, usually part of an operand field
/ Reserved bit, invalid instruction form if encoded as 1
? Allocated for implementation-dependent use.
3-26
Table 3-11. Instructions Sorted by Mnemonic (continued)
Mnemonic
)
orc.
OR with Complement and record CR
ori
OR Immediate
oris
OR Immediate Shifted
rfci
Return From Critical Interrupt
5
rfdi
Return From Debug Interrupt
rfi
Return From Interrupt
rlwimi
Rotate Left Word Immed then Mask Insert
rlwimi.
Rotate Left Word Immed then Mask Insert and record CR
rlwinm
Rotate Left Word Immed then AND with Mask
rlwinm.
Rotate Left Word Immed then AND with Mask and record CR
rlwnm
Rotate Left Word then AND with Mask
rlwnm.
Rotate Left Word then AND with Mask and record CR
sc
System Call
slw
Shift Left Word
slw.
Shift Left Word and record CR
sraw
Shift Right Algebraic Word
sraw.
Shift Right Algebraic Word and record CR
srawi
Shift Right Algebraic Word Immediate
srawi.
Shift Right Algebraic Word Immediate and record CR
srw
Shift Right Word
srw.
Shift Right Word and record CR
stb
Store Byte
stbu
Store Byte with Update
stbux
Store Byte with Update Indexed
stbx
Store Byte Indexed
1
stfd
Store Floating-Point Double
1
stfdu
Store Floating-Point Double with Update
1
stfdux
Store Floating-Point Double with Update Indexed
e200z3 Power Architecture Core Reference Manual, Rev. 2
Instruction
Freescale Semiconductor

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