Freescale Semiconductor e200z3 Reference Manual page 384

Nexus3/Nexus2+ Module
Table 10-16 shows the mapping of RWD bytes to byte lanes of the AHB read and write data buses.
Transfer Size
and byte offset
Byte @000
Byte @001
Byte @010
Byte @011
Byte @100
Byte @101
Byte @110
Byte @111
Half @000
Half @010
Half @100
Half @110
Word @000
Word @100
Doubleword @000
First RWD pass
Second RWD pass
Note:
"—" indicates byte lanes which will contain unused data.
10.4.7 Read/Write Access Address Register (RWA)
The read/write access address register, shown in
accessed when initiating a read or a write access.
31
Field
Reset
R/W
Number
10-18
Table 10-16. RWD byte lane data placement
RWA(2:0)
31–24
0 0 0 —
0 0 1 —
0 1 0 —
0 1 1 —
1 0 0 —
1 0 1 —
1 1 0 —
1 1 1 —
0 0 0 —
0 1 0 —
1 0 0 —
1 1 0 —
0 0 0 AHB[31–24]
1 0 0 AHB[63–56]
0 0 0 —
AHB[31–24]
AHB[63–56]
Figure 10-10. Read/Write Access Address Register (RWA)
e200z3 Power Architecture Core Reference Manual, Rev. 2
RWD
23–16 15–8
—
—
—
—
—
—
—
—
— AHB[15–8]
— AHB[31–24]
— AHB[47–40]
— AHB[63–56]
AHB[23–16] AHB[15–8]
AHB[55–48] AHB[47–40]
—
AHB[23–16] AHB[15–8]
AHB[55–48] AHB[47–40]
Figure 10-10, provides the system bus address to be
Read/Write Data
All zeros
Read/Write
0xA
7–0
— AHB[7–0]
— AHB[15–8]
— AHB[23–16]
— AHB[31–24]
— AHB[39–32]
— AHB[47–40]
— AHB[55–48]
— AHB[63–56]
AHB[7–0]
AHB[23–16]
AHB[39–32]
AHB[55–48]
AHB[7–0]
AHB[39–32]
— —
AHB[7–0]
AHB[39–32]
0
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