Freescale Semiconductor e200z3 Reference Manual

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e200z3 Power Architecture™

Core Reference Manual

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e200z3

e200z335

e200z3coreRM

Rev. 2

06/2008

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Page 1 Power Architecture™ Core Reference Manual Supports e200z3 e200z335 e200z3coreRM Rev. 2 06/2008...
Page 2 Freescale Semiconductor Japan Ltd. or for any other application in which the failure of the Freescale Semiconductor product Headquarters could create a situation where personal injury or death may occur. Should Buyer...
Page 3: Table Of Contents
User Instruction Set ....................1-15 1.7.1.2 Supervisor Instruction Set..................1-15 1.7.2 Memory Subsystem ....................1-15 1.7.3 Interrupt Handling...................... 1-15 1.7.4 Memory Management....................1-16 1.7.5 Reset........................... 1-16 1.7.6 Little-Endian Mode....................1-16 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 4: Paragraph Page
Misaligned Instruction Fetch Syndrome..............2-25 2.9.3 Precise External Termination Error Syndrome............2-25 2.9.4 e200z3-Specific Interrupt Registers................2-26 2.9.4.1 Debug Save/Restore Register 0 (DSRR0) ............. 2-26 2.9.4.2 Debug Save/Restore Register 1 (DSRR1) ............. 2-26 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 5 Process ID Register (PID0)..................2-69 2.17 Support for Fast Context Switching................2-69 2.17.1 Context Control Register (CTXCR) ................2-70 2.18 SPR Register Access...................... 2-70 2.18.1 Invalid SPR References ..................... 2-70 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 6 Unimplemented SPRs and Read-Only SPRs ..............3-16 3.12 Invalid Instruction Forms....................3-17 3.13 Instruction Summary...................... 3-17 3.13.1 Instruction Index Sorted by Mnemonic ..............3-18 3.13.2 Instruction Index Sorted by Opcode ................3-29 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 7 Exception Recognition and Priorities ................4-28 4.7.1 Interrupt Priorities...................... 4-29 Interrupt Processing ....................... 4-32 4.8.1 Enabling and Disabling Exceptions................4-33 4.8.2 Returning from an Interrupt Handler ................. 4-33 Process Switching ......................4-34 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 8 MAS Register Updates ..................5-14 Effect of Hardware Debug on MMU Operation ............5-15 Chapter 6 Instruction Pipeline and Execution Timing Overview of Operation ....................6-1 6.1.1 Control Unit ......................... 6-2 e200z3 Power Architecture Core Reference Manual, Rev. 2 viii Freescale Semiconductor...
Page 9 JTAG ID Signals ......................7-29 Internal Signals ......................7-30 Timing Diagrams ......................7-30 7.5.1 Processor Instruction/Data Transfers ................. 7-30 7.5.1.1 Basic Read Transfer Cycles ................... 7-32 7.5.1.2 Read Transfer with Wait State ................7-33 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 10 OnCE Internal Interface Signals ................9-16 9.5.3.1 CPU Address and Attributes.................. 9-16 9.5.3.2 CPU Data ....................... 9-16 9.5.4 OnCE Interface Signals ..................... 9-16 9.5.5 OnCE Controller and Serial Interface................ 9-18 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 11 Data Trace Start Address 1 and 2 Registers (DTSA1 and DTSA2) ......10-23 10.4.11 Data Trace End Address Registers 1 and 2 (DTEA1 and DTEA2)......10-23 10.5 Nexus3/Nexus2+ Register Access Through JTAG/OnCE........... 10-24 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 12 DTM Operation......................10-41 10.8.3.1 DTM Queueing....................10-41 10.8.3.2 Relative Addressing..................... 10-41 10.8.3.3 Data Trace Windowing ..................10-41 10.8.3.4 Data Access/Instruction Access Data Tracing............. 10-41 10.8.3.5 e200z6e200z3 Bus Cycle Special Cases.............. 10-41 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 13 JTAG Sequence for Accessing Internal Nexus Registers ........10-58 10.16.2 JTAG Sequence for Read Access of Memory-Mapped Resources ......10-59 10.16.3 JTAG Sequence for Write Access of Memory-Mapped Resources......10-59 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor xiii...
Page 14 Contents Paragraph Page Number Title Number e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 15 Data Address Compare Registers (DAC1–DAC2) ............... 2-34 2-31 Data Value Compare Registers (DVC1–DVC2) ..............2-34 2-32 DBCNT Register........................2-35 2-33 DBCR0 Register ........................2-36 2-34 Debug Control Register 1 (DBCR1) ..................2-38 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 16 Victim Selection ........................5-9 MMU Assist Registers Summary ..................5-14 e200z3 Block Diagram......................6-2 Pipeline Diagram........................6-4 Instruction Buffers ........................6-6 Branch Target Buffer....................... 6-7 Basic Pipeline Flow, Single-Cycle Instructions ..............6-8 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 17 7-23 Read and Write Transfers: Instruction Read with Error, Data Read, Write, Full Pipelining ........................7-52 7-24 Data Read with Error, Data Write Retracted, Instruction Read, Full Pipelining ....7-53 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 18 Error Message Format......................10-23 10-17 Indirect Branch Message (History) Format ................ 10-26 10-18 Indirect Branch Message Format ..................10-26 10-19 Direct Branch Message Format................... 10-26 10-20 Resource Full Message Format................... 10-27 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 19 Watchpoint Message Format....................10-40 10-39 Error Message Format......................10-41 10-40 Watchpoint Message and Watchpoint Error Message............10-41 10-41 Error Message Format......................10-46 10-42 Single-Pin MSEO Transfers....................10-49 10-43 Dual-Pin MSEO Transfers ....................10-50 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 20 Figures Figure Page Number Title Number e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 21 MAS2—EPN and Page Attributes..................2-58 2-32 MAS3—RPN and Access Control ..................2-59 2-33 MAS4—Hardware Replacement Assist Configuration Register.......... 2-59 2-34 MAS6—TLB Search Context Register 0................2-60 2-35 System Response to Invalid SPR Reference................. 2-61 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 22 Fixed-Interval Timer Interrupt Register Settings ..............4-19 4-21 Watchdog Timer Interrupt Register Settings................. 4-20 4-22 Data TLB Error Interrupt Register Settings ................4-21 4-23 Instruction TLB Error Interrupt Register Settings ..............4-21 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 23 4-33 MSR Setting Due to Interrupt ....................4-32 TLB Maintenance Programming Model ................. 5-2 Page Size (for e200z3 Core) and EPN Field Comparison ............5-5 TLB Entry Bit Fields for e200z3 .................... 5-9 tlbivax EA Bit Definitions ....................5-11 TLB Entry 0 Values after Reset .................... 5-13 MMU Assist Register Field Updates ..................
Page 24 DS Field Descriptions ......................10-14 10-13 RWCS Field Descriptions ....................10-15 10-14 Read/Write Access Status Bit Encodings................10-15 10-15 RWD data placement for Transfers..................10-16 10-16 RWD byte lane data placement ................... 10-17 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 25 Data Write Message Example (8 MDO/2 MSEO).............. 10-54 10-41 Accessing Internal Nexus3 Registers through JTAG/OnCE..........10-54 10-42 Accessing Memory-Mapped Resources (Reads) ..............10-55 10-43 Accessing Memory-Mapped Resources (Writes) ............... 10-55 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 26 Tables Table Page Number Title Number e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 27 About This Book The primary objective of this user’s manual is to describe the functionality of the e200z3 embedded microprocessor core for software and hardware developers. This book is intended as a companion to the EREF: A Programmer's Reference Manual for Freescale Book E Processors (hereafter referred to as EREF).
Page 28: General Information
• Chapter 10, “Nexus3/Nexus2+ Module,” describes the e200z3 Nexus3 module, which provides real-time development capabilities for e200z3 processors in compliance with the IEEE-ISTO Nexus 5001-2003 standard. • This book also includes an index. Suggested Reading This section lists additional reading that provides background for the information in this manual as well as general information about the architecture.
Page 29: Related Documentation
EREF: A Programmer's Reference Manual for Freescale Book E Processors (EREF)—This book provides a higher-level view of the programming model as it is defined by Book E, the Freescale Book E implementation standards, and the e200z3 microprocessor. • Reference manuals—These books provide details about individual implementations and are intended for use with the EREF.
Page 30: Terminology Conventions
Table ii. Acronyms and Abbreviated Terms Term Meaning Condition register Count register Data control register DTLB Data translation lookaside buffer Effective address e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 31 Translation lookaside buffer UIMM Unsigned immediate value UISA User instruction set architecture Virtual address Variable-length encoding Register used primarily for indicating conditions such as carries and overflows for integer operations e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 32 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 33: E200Z335 Core Complex Overview
(EIS) Overview of the e200z3 and e200z335 The e200z3 and e200z335 processor family is a set of CPU cores that are low-cost implementations of Power Architecture technology for embedded processors. e200z3 and e200z335 processors are designed for deeply embedded control applications that require low-cost solutions rather than maximum performance.
Page 34 Unit + x ÷ + x ÷ EA Calc Optional Write-Back Stage Extension SPRs Data Bus Interface Unit Single-Instruction, In-Order Write Back Address Data Control e200z3 Figure 1-1. Block Diagram e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 35 Nexus Class 2+ module is integrated in the e200z335. The e200z3 platform is specified in such a way that functional units can be added or removed. The e200z3 can be configured with a powerful vectored interrupt controller and one or more IP slave interfaces, as well as support for configured memory units.
Page 36: Features
— Dynamic power management of execution units • e200z3 and e200z335-specific debug interrupt. The e200z3 family implements the debug interrupt as defined by the Power ISA with the following changes: — When the debug instructions are enabled (HID0[DAPUEN] = 1), debug is no longer a critical interrupt, but uses DSRR0 and DSRR1 for saving machine state on context switch.
Page 37: Programming Model
Register Set Figure 1-3 shows the e200z3 and e200z335 register set, indicating which registers are accessible in supervisor mode and which are accessible in user mode. The number to the left of the special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register. (For example, the integer exception register (XER) is SPR 1.)
Page 38 USPRG0 is a separate physical register from SPRG0. EIS–specific registers; not part of the Power ISA. IVOR9 (handles auxiliary processor unavailable interrupt) is defined by the EIS but not supported by the e200z335. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 39: Instruction Set
The Power ISA instruction set for 32-bit embedded implementations. This is composed primarily of the user-level instructions defined by the user instruction set architecture (UISA). The e200z3 does not include the Power ISA floating-point, load string, or store string instructions.
Page 40: Vle Category
The core supports an extended exception handling model, with nested interrupt capability and extensive interrupt vector programmability. The following sections define the interrupt model, including an overview of interrupt handling as implemented on the e200z3 core, a brief description of the interrupt classes, and an overview of the registers involved in the processes.
Page 41: Interrupt Handling
No instruction following the instruction in the save/restore register has executed. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 42: Interrupt Types
1.5.3 Interrupt Types The e200z3 core processes all interrupts as either debug, critical, or noncritical types. Separate control and status register sets are provided for each type of interrupt. The core handles interrupts from these three categories in the following order of priority: 1.
Page 43 Fixed-interval timer Machine check Watchdog timer Data storage Data TLB error Instruction storage Instruction TLB error External input Debug Alignment 6–31 Reserved Program SPE unavailable Floating-point unavailable SPE data exception e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 1-11...
Page 44: Microarchitecture Summary
Vector to [ p_rstbase[0:19] ] || 0xFFC. Autovectored external and critical input interrupts use this IVOR. Vectored interrupts supply an interrupt vector offset directly. Microarchitecture Summary The e200z3 processor has a four-stage pipeline for instruction execution. 1. Instruction fetch 2. Instruction decode/register file read/effective address calculation 3.
Page 45: Instruction Unit Features
32 × 32 hardware multiplier array that supports single cycle 32 × 32 > 32 multiply • 1.6.3 Load/Store Unit (LSU) Features The e200z3 LSU supports load, store, and load multiple/store multiple instructions: • 32-bit effective address adder for data memory address calculations •...
Page 46: Memory Management Unit (Mmu) Features
1.6.6 Nexus 32+ Module Features The Nexus 3 (Nexus 2+ in e200z335) module provides real-time development capabilities for e200z3 and e200z335 processors in compliance with the IEEE-ISTO Nexus 5001-2003 standard. This module provides development support capabilities without requiring the use of address and data pins for internal visibility.
Page 47: Instruction Set Compatibility
The following sections describe the user and supervisor instruction sets. 1.7.1.1 User Instruction Set The e200z3 core family executes legacy user-mode binaries and object files except for the following: • The e200z3 core supports vector and scalar single-precision floating-point operations. These instructions have different encoding than the original definition of the PowerPC architecture.
Page 48: Memory Management
An overview of the interrupt and exception handling capabilities of the e200z3 core can be found in Section 1.5, “Interrupts and Exception Handling.”...
Page 49 Chapter 2 Register Model This chapter describes the registers of the e200z3 and e200z335 cores. It includes an overview of registers defined by the Book E architecture, highlighting differences in how these registers are implemented in the e200z3 core, and it describes the e200z3-specific registers in detail. Full descriptions of the architecture-defined register set are provided in the EREF.
Page 50 Register Model e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 51 USPRG0 is a separate physical register from SPRG0. EIS-specific registers; not part of the Book E architecture. IVOR9 (handles auxiliary processor unavailable interrupt) is defined by the EIS but not supported by the e200z3. DVC1, DVC2, DBCR4, and DBERC0 are implemented in e200z335 only.
Page 52: Powerpc Book E Registers
Figure 2-1. e200z3 Programmer’s Model PowerPC Book E Registers The e200z3 supports most of the registers defined by Book E architecture. Notable exceptions are the floating-point registers FPR0–FPR31 and the FPSCR. The e200z3 does not support the Book E floating-point architecture in hardware. The GPRs are extended to 64 bits. The Book E registers in the e200z3 are as follows: •...
Page 53 – SPRG0–SPRG7, USPRG0. For software use. See Section 2.10, “Software-Use SPRs (SPRG0–SPRG7 and USPRG0),” for details on these registers. The e200z3 does not allow user-mode access to the SPRG3 register. Book E defines access to SPRG3 as implementation-dependent. – Exception syndrome register (ESR). A syndrome to differentiate between the different kinds of exceptions that can generate the same interrupt.
Page 54: E200Z3-Specific Registers
— The EIS-defined accumulator, which is part of the SPE APU. See Section 2.7.2, “Accumulator (ACC).” • Supervisor-level registers, which are defined in the e200z3 in addition to the Book E registers described in Section 2.1, “PowerPC Book E Registers: —...
Page 55: E200Z3-Specific Device Control Registers
In addition to the SPRs, implementations may also implement one or more device control registers (DCRs). The e200z3 core implements a set of device control registers to perform a parallel signature in the parallel signature unit (PSU). These registers may not be supported by other PowerPC processors. For details, see Section 2.19, “Parallel Signature Unit Registers.”...
Page 56 — Reserved, should be cleared. Wait state (power management) enable. Defined as optional by Book E and implemented in the e200z3. 0 Power management is disabled. 1 Power management is enabled. The processor can enter a power-saving mode when additional conditions are present.
Page 57: Processor Id Register (Pir)
Processor ID Register (PIR) The processor ID for the CPU core is contained in the processor ID register (PIR), shown in Figure 2-3. The contents of PIR reflect the hardware input signals to the e200z3 core. Field — Reset 0000_0000_0000_0000_0000_0000...
Page 58: Processor Version Register (Pvr)
Identifies the processor type. For the e200z3, this field has a value of 0b01_0001. 44–47 Version Identifies the version of the processor and any optional elements. For e200z3, this field has a value of 0010. Distinguishes different system variants; provided by the p_pvrin[16:23] inputs.
Page 59: Registers For Integer Operations
Register Model Field Version Reset SoC-dependent value (determined by p_sysvers[0:31] on the e200z3 core) Read only SPR 1023 Figure 2-5. System Version Register (SVR) SVR specifies a particular implementation of an e200z3-based system. Table 2-4. SVR Field Description Bits Name Description 32–63...
Page 60: Registers For Branch Operations
A specified CR field may be set as the result of either an integer or a floating-point compare instruction (including SPE and SPFP compare instructions). Instructions are provided to perform logical operations on individual CR bits and to test individual CR bits. e200z3 Power Architecture Core Reference Manual, Rev. 2 2-12 Freescale Semiconductor...
Page 61 10011 For SPE and SPFP vector compare and test instructions: 10111 Set to the AND of the result of the compare of the high and low elements. 11011 11111 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-13...
Page 62: Cr Setting For Integer Instructions
4 * cr3 + lt or rB (unsigned comparison). 4 * cr4 + lt 4 * cr5 + lt 4 * cr6 + lt 4 * cr7 + lt e200z3 Power Architecture Core Reference Manual, Rev. 2 2-14 Freescale Semiconductor...
Page 63: Count Register (Ctr)
The link register, shown in Figure 2-9, provides the branch target address for the branch conditional to LR instructions, and it holds the return address after branch and link instructions. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-15...
Page 64: Spe And Spfp Apu Registers
FG FX FINV FDBZ FUNF FOVF — FINXE FINVE FDBZE FUNFE FOVFE FRMC Reset 0000_0000_0000_0000 SPR 512 Figure 2-10. Signal Processing and Embedded Floating-Point Status and Control Register (SPEFSCR) e200z3 Power Architecture Core Reference Manual, Rev. 2 2-16 Freescale Semiconductor...
Page 65 FUNFS remains set until it is cleared by an mtspr specifying SPEFSCR. FOVFS Embedded floating-point overflow sticky flag. Set when a floating-point instruction sets FOVFH or FOVF. FOVFS remains set until it is cleared by an mtspr specifying SPEFSCR. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-17...
Page 66 Description MODE Embedded floating-point operating mode. 0 Default hardware results operating mode. The e200z3 supports only mode 0. 1 IEEE754 hardware results operating mode (not supported by the e200z3). Controls the operating mode of the embedded floating-point APU. Software should read the value of this bit after writing it to determine whether the implementation supports the selected mode.
Page 67: Accumulator (Acc)
Section 2.8.1.5, “Data Exception Address Register (DEAR)” • Section 2.8.1.6, “Interrupt Vector Prefix Register (IVPR)” • Section 2.8.1.7, “Interrupt Vector Offset Registers (IVORs)” • Section 2.9, “Exception Syndrome Register (ESR)” e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-19...
Page 68: Save/Restore Register 0 (Srr0)
The instruction is interrupt-specific; for details, see Chapter 4, “Interrupts and Exceptions.” When rfci executes, instruction execution continues at the address in CSRR0. CSRR0 and CSRR1 are not affected by rfi or rfdi. e200z3 Power Architecture Core Reference Manual, Rev. 2 2-20 Freescale Semiconductor...
Page 69: Critical Save/Restore Register 1 (Csrr1)
The value contained in the vector offset field of the IVOR selected for a particular interrupt type is concatenated with the value in the IVPR to form an instruction address from which execution is to begin. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-21...
Page 70: Interrupt Vector Offset Registers (Ivors)
Reserved, should be cleared. 61–63 Context selector (e200z3-specific). When multiple hardware contexts are supported, this field is used to select an operating context for the interrupt handler. This value is loaded into the CURCTX field of the context control register (CTXCR) as part of the interrupt vectoring process. When multiple hardware contexts are not supported, CS is not implemented and is read as zero.
Page 71: Exception Syndrome Register (Esr)
IVOR6 406 Program IVOR7 407 Floating-point unavailable IVOR8 408 System call IVOR9 409 Auxiliary processor unavailable. (Defined by the EIS but not supported in the e200z3.) IVOR10 410 Decrementer IVOR11 411 Fixed-interval timer interrupt IVOR12 412 Watchdog timer interrupt IVOR13...
Page 72 — Data cache locking Data storage Instruction cache locking Data storage` Auxiliary processor operation. (unused in the e200z3) Alignment, data storage, data TLB, program Unimplemented operation exception Program Byte ordering exception Data storage Program imprecise exception. Unused in the e200z3 —...
Page 73: Vle Mode Instruction Syndrome
Instruction storage, instruction TLB External termination error (precise) Data storage, instruction storage When optional cache is present. Unused on e200z3. 2.9.1 VLE Mode Instruction Syndrome ESR[VLEMI] indicates when an interrupt is caused by a VLE instruction. This syndrome bit is set on an exception associated with execution or attempted execution of a VLE instruction.
Page 74: E200Z3-Specific Interrupt Registers
Register Model 2.9.4 e200z3-Specific Interrupt Registers In addition to the Book E-defined interrupt registers, the e200z3 implements DSRR0 and DSRR1 to facilitate handling debug interrupts and the EIS-defined MCSR to facilitate handling machine check interrupts. 2.9.4.1 Debug Save/Restore Register 0 (DSRR0)
Page 75: Software-Use Sprs (Sprg0-Sprg7 And Usprg0)
• SPRG3—Written only in supervisor mode. It is readable in supervisor mode, but whether it can be read in user mode depends on the implementation. It is not readable in user mode on the e200z3. • SPRG4–SPRG7—Written only in supervisor mode. They are readable in supervisor or user mode.
Page 76: Timer Registers
USPRG0 256 Read/Write User/Supervisor Figure 2-22. Software-Use SPRs (SPRG0–SPRG7 and USPRG0) User-mode access to SPRG3 is defined by Book E as implementation-dependent. It is not supported in the e200z3. Software-use SPRs are read into a GPR using mfspr and are written using mtspr.
Page 77: Timer Control Register (Tcr)
42 43 46 47 50 51 Field WP WRC WIE DIE FP FIE ARE — WPEXT FPEXT — Reset All zeros SPR 340 Figure 2-24. Timer Control Register (TCR) e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-29...
Page 78: Timer Status Register (Tsr)
TSR in detail. TSR[WRS] is defined as implementation-dependent. NOTE Register fields designated as write-1-to-clear are cleared only by writing ones to them. Writing zeros to them has no effect. e200z3 Power Architecture Core Reference Manual, Rev. 2 2-30 Freescale Semiconductor...
Page 79: Time Base (Tbu And Tbl)
2-26, is composed of two 32-bit registers, the time base upper (TBU) concatenated on the right with the time base lower (TBL). The time base registers provide timing functions e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-31...
Page 80 TB is constant, the TB can be used as a source of values that increase at a constant rate, such as for time stamps in trace entries. e200z3 Power Architecture Core Reference Manual, Rev. 2 2-32 Freescale Semiconductor...
Page 81: Decrementer Register
Field Decrementer auto-reload value Reset Undefined on m_por assertion, unchanged on p_reset_b assertion SPR 54 Figure 2-28. Decrementer Auto-Reload Register (DECAR) e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-33...
Page 82: Debug Registers
To blocks of addresses specified by the combination of the IAC3 and IAC4. Because all instruction addresses must be word-aligned, the two low-order bits of the IACs are reserved and do not participate in the comparison with the instruction address. e200z3 Power Architecture Core Reference Manual, Rev. 2 2-34 Freescale Semiconductor...
Page 83: Data Address Compare Registers (Dac1-Dac2)
B0 address B1 address B2 address B3 address B4 address B5 address B6 Reset All zeros SPR 318 (DVC1); SPR 319 (DVC2) Figure 2-31. Data Value Compare Registers (DVC1–DVC2) e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-35...
Page 84: Debug Counter Register (Dbcnt)
The debug status register (DBSR) records debug exceptions while internal or external debug mode is enabled. To ensure that any alterations enabling/disabling debug events are effective, the e200z3 requires that a context synchronizing instruction follow an mtspr that updates a DBCR or DBSR. The context synchronizing instruction may or may not be affected by the alteration.
Page 85 10 p_resetout_b set by debug reset control. Allows external device to initiate processor reset. 11 Reserved. ICMP Instruction complete debug event enable. 0 ICMP debug events are disabled. 1 ICMP debug events are enabled. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-37...
Page 86 0 DEVT2 debug events are disabled. 1 DEVT2 debug events are enabled. DCNT1 Debug counter 1 debug event enable. 0 counter 1 debug events are disabled. 1 counter 1 debug events are enabled. e200z3 Power Architecture Core Reference Manual, Rev. 2 2-38 Freescale Semiconductor...
Page 87: Debug Control Register 1 (Dbcr1)
Reset by processor reset p_reset_b if DBCR0[EDM]=0, as well as unconditionally by m_por. If DBCR0[EDM]=1, DBERC0 masks off hardware-owned resources from reset by p_reset_b and only software-owned resources indicated by DBERC0 will be reset by p_reset_b. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-39...
Page 88 00 IAC1 debug events are based on effective address. 01 Unimplemented in the e200z3 (Book E real address compare), no match can occur. 10 IAC1 debug events are based on effective address and can occur only if MSR[IS] = 0.
Page 89: Debug Control Register 2 (Dbcr2)
00 IAC4 debug events are based on effective address. 01 Unimplemented in the e200z3 (Book E real address compare), no match can occur. 10 IAC4 debug events are based on effective address and can occur only if MSR[IS] = 0.
Page 90 00 DAC1 debug events are based on effective address. 01 Unimplemented in the e200z3 (Book E real address compare), no match can occur. 10 DAC1 debug events are based on effective address and can occur only if MSR[DS] = 0.
Page 91: Debug Control Register 3 (Dbcr3)
Debug Control Register 3 (DBCR3) DBCR3, shown in Figure 2-36, is an e200z3 implementation-specific register to enable and configure the debug counter and debug counter events. For counter operation, the specific debug events that cause counters to decrement are specified in DBCR3.
Page 92 All zeros IAC1C2 IAC2C2 IAC3C2 IAC4C2 DAC1RC2 DAC1WC2 DAC2RC2 DAC2WC2 Reset All zeros DEVT1T1 DEVT2T1 IAC1T1 IAC3T1 DAC1RT1 DAC1WT1 CNT2T1 CONFIG Reset All zeros SPR 561 Figure 2-36. DBCR3 Register e200z3 Power Architecture Core Reference Manual, Rev. 2 2-44 Freescale Semiconductor...
Page 93 1 Counting RET debug events by counter 1 is enabled. DEVT1C2 External debug event 1 count 2 enable. 0 Counting DEVT1 debug events by counter 2 is disabled. 1 Counting DEVT1 debug events by counter 2 is enabled. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-45...
Page 94 1 An IAC1 debug event triggers counter 1 operation. IAC3T1 Instruction address compare 3 trigger counter 1 enable. 0 No effect. 1 An IAC3 debug event triggers counter 1 operation. e200z3 Power Architecture Core Reference Manual, Rev. 2 2-46 Freescale Semiconductor...
Page 95 DBCR3 is loaded with a value that prevents the particular event from being counted. When the mtspr finishes executing, a debug event is posted, but the e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-47...
Page 96: Debug Control Register 4 (Dbcr4) (E200Z335 Only)
DVC2C controls whether DVC2 data value comparisons utilize the normal BookE operation, or an alternate "inverted compare" operation. In inverted polarity mode, data value compares perform a not-equal comparison. See details in the DBCR2 register definition 4:31 — Reserved e200z3 Power Architecture Core Reference Manual, Rev. 2 2-48 Freescale Semiconductor...
Page 97: Debug Status Register (Dbsr)
Instruction complete debug event. Set if an instruction complete debug event occurs. Branch taken debug event. Set if an branch taken debug event occurs. IRPT Interrupt taken debug event. Set if an interrupt taken debug event occurs. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-49...
Page 98: Debug External Resource Control Register (Dberc0)
Reserved, should be cleared. 61–62 DAC_OFS Data Address Compare Offset (e200z335 only, reserved on e200z3) Indicates offset-1 of saved DSRR0 value from the address of the load or store instruction which took a DAC Debug exception, unless a simultaneous DTLB or DSI error occurs, in which case this field is set to 2‘b00 and DBSR[IDE] is set to 1.
Page 99 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SPR - 569; Read-only by Software; Reset - Unaffected by p_reset_b, cleared by m_por or while in the test-logic-reset OnCE controller state Figure 2-39. DBERC0 Register e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-51...
Page 100 0 - Event owned by hardware debug. No mtspr access by software to DBCR0[TRAP] or TRAP DBSR[TRAP] fields. 1 - Event owned by software debug. DBCR0[TRAP] and DBSR[TRAP] are software readable/writeable. e200z3 Power Architecture Core Reference Manual, Rev. 2 2-52 Freescale Semiconductor...
Page 101 0 - Event owned by hardware debug. No mtspr access by software to DBCR0[DEVT1] or DEVT1 DBSR[DEVT1] fields. 1 - Event owned by software debug. DBCR0[DEVT1] and DBSR[DEVT1] are software readable/writeable. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-53...
Page 102 27:30 — Reserved Freeze Timer Debug Control 0 - DBCR0[FT] owned by hardware debug. No access by software. 1 - DBCR0[FT] owned by software debug. DBSR[FT] is software readable/writeable. e200z3 Power Architecture Core Reference Manual, Rev. 2 2-54 Freescale Semiconductor...
Page 103 DBCR1[IAC1US, IAC1ER] DBSR[IAC1] IAC2, DBCR0[IAC2], DBCR1[IAC2US, IAC2ER] DBSR[IAC2] DBCR1[IAC12M] IAC3, DBCR0[IAC3], DBCR1[IAC3US, IAC3ER] DBSR[IAC3] IAC4, DBCR0[IAC4], DBCR1[IAC4US, IAC4ER] DBSR[IAC4] DBCR1[IAC34M] DAC1, DVC1 DBCR0[DAC1], DBCR2[DAC1US, DAC1ER, DVC1M, DVC1BE] DBCR4[DVC1C] DBSR[DAC1, DAC_OFST] e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-55...
Page 104 RETC1, DEVT1T1, DEVT2T1, IAC1T1, IAC3T1, DAC1RT1, DAC1WT1, CNT2T1] DBSR[DCNT1, CNT1TRG], DBCNT[CNT1] DBCR0[DCNT2], DBCR3[DEVT1C2, DEVT2C2, ICMPC2, IAC1C2, IAC2C2, IAC3C2, IAC4C2, DAC1RC2, DAC1WC2, DAC2RC2, DAC2WC2] DBSR[DCNT2], DBCNT[CNT2] DBCR3[CONFIG] DBCR0[CIRPT], DBSR[CIRPT] DBCR0[CRET], DBSR[CRET] e200z3 Power Architecture Core Reference Manual, Rev. 2 2-56 Freescale Semiconductor...
Page 105: Hardware Implementation-Dependent Registers
All zeros — TBEN SEL_TBCLK DCLREE DCLRCE CICLRDE MCCLRDE DAPUEN — Reset All zeros SPR 1008 Figure 2-40. Hardware Implementation-Dependent Register 0 (HID0) HID0 fields are described in Table 2-25. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-57...
Page 106 Debug interrupt clears MSR[EE]. Controls whether debug interrupts force external input interrupts to be disabled, or whether they remain unaffected. 0 MSR[EE] unaffected by debug interrupt. 1 MSR[EE] cleared by debug interrupt. e200z3 Power Architecture Core Reference Manual, Rev. 2 2-58 Freescale Semiconductor...
Page 107: Hardware Implementation-Dependent Register 1 (Hid1)
The HID1 register is used for bus configuration and system control. HID1 is shown in Figure 2-41. Field — – Reset All zeros SPR 1009 Figure 2-41. Hardware Implementation-Dependent Register 1 (HID1) HID1 fields are described in Table 2-26. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-59...
Page 108 “Memory Synchronization and Reservation Instructions.” 57–62 — Reserved, should be cleared. Address retraction disable. 0 Address retraction enabled. 1 Address retraction disabled. Controls Address Retraction operation. For details, see Section 7.5.3, “Address Retraction.” e200z3 Power Architecture Core Reference Manual, Rev. 2 2-60 Freescale Semiconductor...
Page 109: Branch Target Buffer (Btb) Registers
2.15.1 L1 Cache Configuration Register 0 (L1CFG0) The L1 cache configuration register 0 (L1CFG0) provides information on how not to configure the e200z3 cache design. For e200z3, reads of this register return a value of all zeros. e200z3 Power Architecture Core Reference Manual, Rev. 2...
Page 110: Mmu Registers
Register Model 2.16 MMU Registers This section describes the e200z3 registers for setting up and maintaining the TLBs. 2.16.1 MMU Control and Status Register 0 (MMUCSR0) MMUCSR0, shown in Figure 2-43, controls the state of the MMU. Field — TLB1_FI —...
Page 111: Tlb Configuration Registers (Tlbncfg)
2-45, provides information about the configuration of TLB0. Because the e200z3 MMU design does not implement TLB0, this register reads as all zeros. It is supplied to allow software to query it in a way compatible with other Freescale Book E designs.
Page 112: Tlb Configuration Register 1 (Tlb1Cfg)
1 All page sizes between MINSIZE and MAXSIZE are supported. 50–51 — Reserved, should be cleared. 52–63 NENTRY Number of entries. 0x8 - TLB1 contains 8 entries. 0x010TLB1 contains 16 entries. e200z3 Power Architecture Core Reference Manual, Rev. 2 2-64 Freescale Semiconductor...
Page 113: Mmu Assist Registers (Mas0-Mas4, Mas6)
TLBs. The MAS registers can be read or written using the mfspr and mtspr instructions. The e200z3 does not implement the MAS5 register, which is present in other Freescale Book E designs, because the tlbsx instruction only searches based on a single SPID value.
Page 114 Access: Supervisor read/write Reset Undefined 51 52 54 55 56 57 59 60 61 62 63 — VLE W I M G E Figure 2-49. MMU Assist Register 2 (MAS2) e200z3 Power Architecture Core Reference Manual, Rev. 2 2-66 Freescale Semiconductor...
Page 115 Cache inhibited. 0 This page is cacheable. 1 This page is cache-inhibited. Memory coherence required.The e200z3 does not support the memory coherence required attribute, and thus it is ignored. 0 Memory coherence is not required. 1 Memory coherence is required.
Page 116 32–33 — Reserved, should be cleared. 34–35 TLBSELD Default TLB selected. 01 TLB1 (ignored by the e200z3, should be written to 01 for future compatibility) 36–43 — Reserved, should be cleared. 44–47 TIDSELD TID default selection value. 4-bit field that specifies which of the current PID registers should be used to load the MAS1[TID] field on a TLB miss exception.
Page 117: Process Id Register (Pid0)
Support for Fast Context Switching To provide real-time capabilities for embedded systems, future versions of the e200z3 core will include optional hardware support for fast context switching. The initial version of the e200z3 does not implement additional register contexts. e200z3 Power Architecture Core Reference Manual, Rev. 2...
Page 118: Context Control Register (Ctxcr)
2.17.1 Context Control Register (CTXCR) The future versions of the e200z3 core may include optional hardware support for fast context switching to provide real-time capabilities for embedded systems. The initial version of e200z3 does not implement additional register contexts. A new privileged 32-bit special-purpose register (SPR) called the context control register (CTXCR) is defined in the core CPU.
Page 119: Special-Purpose Register Summary
1. Not required if counter is not currently enabled. 2.18.3 Special-Purpose Register Summary PowerPC Book E and implementation-specific SPRs for the e200z3 core are listed in Table 2-40. All registers are 32 bits. Register bits are numbered from bit 32–63 (most significant to least significant).
Page 120 Interrupt vector offset register 4 IVOR5 Interrupt vector offset register 5 IVOR6 Interrupt vector offset register 6 IVOR7 Interrupt vector offset register 7 IVOR8 Interrupt vector offset register 8 e200z3 Power Architecture Core Reference Manual, Rev. 2 2-72 Freescale Semiconductor...
Page 121 SPEFSCR SPE APU status and control register SPRG0 SPR general 0 SPRG1 SPR general 1 SPRG2 SPR general 2 SPRG3 SPR general 3 SPRG4 SPR general 4 Read only e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-73...
Page 122: Reset Settings
IVOR9 handles the auxiliary processor unavailable interrupt. This interrupt is defined by the EIS but not supported in the e200z3; therefore, use of IVOR9 is not supported in the e200z3. TSR is read using mfspr, but it cannot be directly written. Instead, TSR bits corresponding to 1 bits in the GPR can be cleared using mtspr.
Page 123 Register Model Table 2-41. Reset Settings for e200z3 Resources (continued) Resource System Reset Setting Unaffected BUCSR 0x0000_0000 CSRR0 Unaffected CSRR1 Unaffected Unaffected CTXCR 000 || NUMCTX || 00_0000_0000_0000_0000_0000_0000 DAC1–DAC2 0x0000_0000 DVC1–DVC2 Unaffected DBCNT Unaffected DBCR0–DBCR3 0x0000_0000 DBSR 0x1000_0000 DEAR Unaffected...
Page 124: Parallel Signature Unit Registers
2.19 Parallel Signature Unit Registers To support applications requiring system integrity checking during operation, the e200z3 provides a Parallel Signature unit to monitor the CPU data read and data write AHB buses and to accumulate a pair of 32-bit MISR signatures of the data values transferred over these buses.
Page 125: Parallel Signature Control Register (Pscr)
2-55, controls operation of the parallel signature unit. 59 60 Field — CNTEN — RDEN WREN INIT Reset All zeros DCR 272 Figure 2-55. Parallel Signature Control Register (PSCR) e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-77...
Page 126: Parallel Signature Status Register (Pssr)
Figure 2-57, provides signature information for the high word (bits 63–32) of the AHB data read and data write buses. Writing PSHR initializes a seed value before enabling signature e200z3 Power Architecture Core Reference Manual, Rev. 2 2-78 Freescale Semiconductor...
Page 127: Parallel Signature Low Register (Pslr)
PSCR[INIT] can also be used to clear PSCTR. PSCTR is unaffected by system reset, thus should be initialized by software before performing parallel signature operations. Field Counter Reset Unaffected DCR 276 Figure 2-59. Parallel Signature Counter Register (PSCTR) e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 2-79...
Page 128: Parallel Signature Update High Register (Psuhr)
(PSLR) using the data value written. Writing to this register causes PSCTR to increment. Field Low signature update data Reset Unaffected Write only DCR 278 Figure 2-61. Parallel Signature Update Low Register (PSULR) e200z3 Power Architecture Core Reference Manual, Rev. 2 2-80 Freescale Semiconductor...
Page 129: Instruction Model
This chapter provides additional information about the Book E architecture as it relates specifically to the e200z3 and e200z335 cores. The e200z3 is a 32-bit implementation of the Book E architecture. The Book E architecture specification includes a recognition that different processor implementations may require clarifications, extensions, or deviations from the architectural descriptions.
Page 130: E200Z3 Floating-Point Implementation
Unsupported Instructions and Instruction Forms Because the e200z3 is a 32-bit Book E core, all of the instructions defined for 64-bit implementations of the Book E architecture are illegal on the e200z3 and cause an illegal instruction exception type program interruption the e200z3.
Page 131: 3.4 Implementation-Specific Instructions
The e200z3 CPU takes an illegal instruction interrupt for unsupported DCR values 3.5 BookE Instruction Extensions The variable length encoding (VLE) provides an extension to 32-bit PowerPC Book E. There are additional operations defined using an alternate instruction encoding to enable reduced code footprint.
Page 132: 3.6 Memory Access Alignment Support
[LR,CTR][32:62] || 0b0. 3.6 Memory Access Alignment Support The e200z3 core provides hardware support for unaligned memory accesses. However, there is a performance degradation for accesses that cross a 64-bit (8 byte) boundary. For these cases, the throughput of the load/store unit is degraded to one misaligned load every 2 cycles. Stores misaligned across a 64-bit (8 byte) boundary can be translated at a rate of 2 cycles per store.
Page 133: Branch Prediction
The e200z3 allows lwarx and stwcx. to access a page marked as write-through required without invoking a data storage interrupt. As Book E allows, the e200z3 does not require the EAs for a stwcx. and the preceding lwarx to be to the same reservation granule.
Page 134: E200Z3-Specific Instructions
3.10.2 Debug APU The e200z3 implements the Freescale Book E debug APU to support the ability to handle the debug interrupt as an additional interrupt level. To support this interrupt level, the Return from Debug Interrupt instruction (rfdi) is defined as part of the debug APU, along with a pair of save/restore registers, DSRR0, and DSRR1.
Page 135: Volatile Context Save/Restore Apu (E200Z335 Only)
Low word versions of signed saturate and signed modulo fractional instructions are not supported. Attempting to execute an opcode corresponding to these instructions causes boundedly undefined results. Table 3-6 defines mnemonic extensions for these instructions. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 136 Add word results to accumulator words (pair of 32-bit sums) Add negated Add negated result to accumulator (64-bit sum) Add negated to accumulator (words) Add negated word results to accumulator words (pair of 32-bit sums) e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 137 Vector Convert Floating-Point from Unsigned Fraction evfscfuf rD,rB Vector Convert Floating-Point from Unsigned Integer evfscfui rD,rB Vector Convert Floating-Point to Signed Fraction evfsctsf rD,rB Vector Convert Floating-Point to Signed Integer evfsctsi rD,rB e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 138 Vector Load Half Word into Half Word Odd Unsigned and Splat evlhhousplat rD,d(rA) Vector Load Half Word into Half Word Odd Unsigned and Splat Indexed evlhhousplatx rD,rA,rB Vector Load Half Word into Half Words Even and Splat evlhhesplat rD,d(rA) e200z3 Power Architecture Core Reference Manual, Rev. 2 3-10 Freescale Semiconductor...
Page 139 Vector Multiply Half Words, Even, Signed, Saturate, Integer and Accumulate Negative into evmhessianw rD,rA,rB Words Vector Multiply Half Words, Even, Unsigned, Modulo, Integer evmheumi rD,rA,rB Vector Multiply Half Words, Even, Unsigned, Modulo, Integer and Accumulate into Words evmheumiaaw rD,rA,rB e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-11...
Page 140 Vector Multiply Word High Signed, Modulo, Integer and Accumulate evmwhsmia rD,rA,rB Vector Multiply Word High Signed, Saturate, Fractional evmwhssf rD,rA,rB Vector Multiply Word High Signed, Saturate, Fractional and Accumulate evmwhssfa rD,rA,rB e200z3 Power Architecture Core Reference Manual, Rev. 2 3-12 Freescale Semiconductor...
Page 141 Vector NOR evnor rD,rA,rB Vector OR evor rD,rA,rB Vector OR with Complement evorc rD,rA,rB Vector Rotate Left Word evrlw rD,rA,rB Vector Rotate Left Word Immediate evrlwi rD,rA,UIMM e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-13...
Page 142 An implementation can restrict the number of bits specified in a mask. The e200z3 limits it to 16 bits, which allows the user to perform bit-reversed address computations for 65536-byte samples. e200z3 Power Architecture Core Reference Manual, Rev. 2...
Page 143: Embedded Vector And Scalar Single-Precision Floating-Point Apu Instructions
Floating-Point Compare Equal efscmpeq evfscmpeq crD,rA,rB Floating-Point Compare Greater Than efscmpgt evfscmpgt crD,rA,rB Floating-Point Compare Less Than efscmplt evfscmplt crD,rA,rB Floating-Point Divide efsdiv evfsdiv rD,rA,rB Floating-Point Multiply efsmul evfsmul rD,rA,rB e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-15...
Page 144: Options For Embedded Floating-Point Apu Implementations
3.11 Unimplemented SPRs and Read-Only SPRs The e200z3 fully decodes the SPR field of mfspr and mtspr instructions. If the SPR specified is undefined and not privileged, an illegal instruction exception is generated. If the SPR specified is undefined and privileged and the CPU is in user mode (MSR[PR] = 1), a privileged instruction exception is generated.
Page 145: Invalid Instruction Forms
For this invalid case, the e200z3 core performs the instruction and updates the register with the load data. In addition, if rA = 0 for any load or store with update instruction, the e200z3 core updates rA (GPR0).
Page 146: Instruction Index Sorted By Mnemonic
Add to Zero Extended with CA & record CR Legend: - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. e200z3 Power Architecture Core Reference Manual, Rev. 2 3-18 Freescale Semiconductor...
Page 147 Condition Register AND with Complement Legend: - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-19...
Page 148 Floating Absolute Value Legend: - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. e200z3 Power Architecture Core Reference Manual, Rev. 2 3-20 Freescale Semiconductor...
Page 149 Floating Multiply-Subtract Single and record CR Legend: - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-21...
Page 150 Floating Square Root Single and record CR Legend: - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. e200z3 Power Architecture Core Reference Manual, Rev. 2 3-22 Freescale Semiconductor...
Page 151 Load Half Word and Zero with Update Indexed Legend: - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-23...
Page 152 Move To FPSCR Bit 0 and record CR Legend: - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. e200z3 Power Architecture Core Reference Manual, Rev. 2 3-24 Freescale Semiconductor...
Page 153 01100 11100 0 OR with Complement Legend: - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-25...
Page 154 Store Floating-Point Double with Update Indexed Legend: - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. e200z3 Power Architecture Core Reference Manual, Rev. 2 3-26 Freescale Semiconductor...
Page 155 Subtract From Extended with CA and record CR Legend: - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-27...
Page 156 XOR and record CR Legend: - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. e200z3 Power Architecture Core Reference Manual, Rev. 2 3-28 Freescale Semiconductor...
Page 157: Instruction Index Sorted By Opcode
- Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. See User’ Manual for the implementation e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-29...
Page 158 - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. See User’ Manual for the implementation e200z3 Power Architecture Core Reference Manual, Rev. 2 3-30 Freescale Semiconductor...
Page 159 - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. See User’ Manual for the implementation e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-31...
Page 160 - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. See User’ Manual for the implementation e200z3 Power Architecture Core Reference Manual, Rev. 2 3-32 Freescale Semiconductor...
Page 161 - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. See User’ Manual for the implementation e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-33...
Page 162 - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. See User’ Manual for the implementation e200z3 Power Architecture Core Reference Manual, Rev. 2 3-34 Freescale Semiconductor...
Page 163 - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. See User’ Manual for the implementation e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-35...
Page 164 - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. See User’ Manual for the implementation e200z3 Power Architecture Core Reference Manual, Rev. 2 3-36 Freescale Semiconductor...
Page 165 - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. See User’ Manual for the implementation e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-37...
Page 166 - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. See User’ Manual for the implementation e200z3 Power Architecture Core Reference Manual, Rev. 2 3-38 Freescale Semiconductor...
Page 167 - Don’t care, usually part of an operand field / Reserved bit, invalid instruction form if encoded as 1 ? Allocated for implementation-dependent use. See User’ Manual for the implementation e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-39...
Page 168 Add Immediate Shifted Book E addme Add to Minus One Extended with CA Book E addme. Add to Minus One Extended with CA & record CR Book E e200z3 Power Architecture Core Reference Manual, Rev. 2 3-40 Freescale Semiconductor...
Page 169 Book E cmpl Compare Logical Book E cmpli Compare Logical Immediate Book E cntlzw Count Leading Zeros Word Book E cntlzw. Count Leading Zeros Word and record CR Book E e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-41...
Page 170 Convert Floating-Point from Signed Integer Scalar SPFP efscfuf Convert Floating-Point from Unsigned Fraction Scalar SPFP efscfui Convert Floating-Point from Unsigned Integer Scalar SPFP efscmpeq Floating-Point Compare Equal Scalar SPFP e200z3 Power Architecture Core Reference Manual, Rev. 2 3-42 Freescale Semiconductor...
Page 171 Store Multiple Volatile SPRs (CR, LR, CTR, and XER) Volatile context save/restore e_sdmvsrrw Store Multiple Volatile SRR (SRR0, SRR1) Volatile context save/restore e_sdmvcsrrw Store Multiple Volatile CSRR (CSRR0, CSRR1) Volatile context save/restore e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-43...
Page 172 Vector Convert Floating-Point from Signed Integer evfscfsi Convert Floating-Point from Signed Integer Vector SPFP evfscfuf Vector Convert Floating-Point from Unsigned Fraction evfscfuf Convert Floating-Point from Unsigned Fraction Vector SPFP e200z3 Power Architecture Core Reference Manual, Rev. 2 3-44 Freescale Semiconductor...
Page 173 Floating-Point Negate Vector SPFP evfssub Vector Floating-Point Subtract evfssub Floating-Point Subtract Vector SPFP evfststeq Vector Floating-Point Test Equal evfststeq Floating-Point Test Equal Vector SPFP evfststgt Vector Floating-Point Test Greater Than e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-45...
Page 174 Multiply Half Words, Even, Guarded, Signed, Modulo, Fractional and Accumulate evmhegsmfan Multiply Half Words, Even, Guarded, Signed, Modulo, Fractional and Accumulate Negative evmhegsmiaa Multiply Half Words, Even, Guarded, Signed, Modulo, Integer and Accumulate e200z3 Power Architecture Core Reference Manual, Rev. 2 3-46 Freescale Semiconductor...
Page 175 Vector Multiply Half Words, Even, Unsigned, Saturate, Integer and Accumulate into Words evmheusianw Vector Multiply Half Words, Even, Unsigned, Saturate, Integer and Accumulate Negative into Words evmhogsmfaa Multiply Half Words, Odd, Guarded, Signed, Modulo, Fractional and Accumulate e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-47...
Page 176 Words evmhousiaaw Vector Multiply Half Words, Odd, Unsigned, Saturate, Integer and Accumulate into Words evmhousianw Vector Multiply Half Words, Odd, Unsigned, Saturate, Integer and Accumulate Negative into Words e200z3 Power Architecture Core Reference Manual, Rev. 2 3-48 Freescale Semiconductor...
Page 177 Vector Multiply Word Signed, Saturate, Fractional evmwssfa Vector Multiply Word Signed, Saturate, Fractional and Accumulate evmwssfaa Vector Multiply Word Signed, Saturate, Fractional and Accumulate evmwssfan Vector Multiply Word Signed, Saturate, Fractional and Accumulate Negative e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-49...
Page 178 Vector Store Word of Two Half Words from Odd evstwhox Vector Store Word of Two Half Words from Odd Indexed evstwwe Vector Store Word of Word from Even evstwwex Vector Store Word of Word from Even Indexed e200z3 Power Architecture Core Reference Manual, Rev. 2 3-50 Freescale Semiconductor...
Page 179 VLE (16-bit opcodes) e_cmph Compare Halfword VLE (16-bit opcodes) e_cmph16i Compare Halfword Immediate VLE (16-bit opcodes) e_cmphl Compare Halfword Logical VLE (16-bit opcodes) e_cmphl16i Compare Halfword Logical Immediate VLE (16-bit opcodes) e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-51...
Page 180 Rotate Left Word & record CR VLE (16-bit opcodes) e_rlwi Rotate Left Word Immediate VLE (16-bit opcodes) e_rlwi. Rotate Left Word Immediate & record CR VLE (16-bit opcodes) e200z3 Power Architecture Core Reference Manual, Rev. 2 3-52 Freescale Semiconductor...
Page 181 Load Half Word Algebraic with Update Indexed Book E lhax Load Half Word Algebraic Indexed Book E lhbrx Load Half Word Byte-Reverse Indexed Book E Load Half Word and Zero Book E e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-53...
Page 182 Multiply Low Word and record CR Book E mullwo Multiply Low Word and record OV Book E mullwo. Multiply Low Word and record OV and CR Book E e200z3 Power Architecture Core Reference Manual, Rev. 2 3-54 Freescale Semiconductor...
Page 183 AND with Complement VLE (32-bit opcodes) se_andi And Immediate VLE (32-bit opcodes) se_b Branch VLE (32-bit opcodes) se_bc Branch Conditional VLE (32-bit opcodes) se_bclri Bit Clear Immediate VLE (32-bit opcodes) e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-55...
Page 184 Move to Alternate Register VLE (32-bit opcodes) se_mtctr Move To Count Register VLE (32-bit opcodes) se_mtlr Move To Link Register VLE (32-bit opcodes) se_mullw Multiply Low Word VLE (32-bit opcodes) e200z3 Power Architecture Core Reference Manual, Rev. 2 3-56 Freescale Semiconductor...
Page 185 Store Byte Book E stbu Store Byte with Update Book E stbux Store Byte with Update Indexed Book E stbx Store Byte Indexed Book E Store Half Word Book E e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-57...
Page 186 Subtract From Zero Extended with CA and record OV Book E subfzeo. Subtract From Zero Extended with CA and record OV and CR Book E tlbivax TLB Invalidate Virtual Address Indexed Book E e200z3 Power Architecture Core Reference Manual, Rev. 2 3-58 Freescale Semiconductor...
Page 187 Book E Trap Word Immediate Book E wrtee Write External Enable Book E wrteei Write External Enable Immediate Book E Book E xor. XOR and record CR Book E e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 3-59...
Page 188 16 bits, which allows the user to perform bit-reversed address computations for 65536-byte samples. Not supported by e200z3 unless the integrated device includes a cache; treated as no-ops, with the exception of dcbz, which results in an alignment interrupt, and dcbi, which is treated as a privileged no-op.
Page 189 This chapter provides a general description of the PowerPC Book E interrupt and exception model and gives details of the additions and changes to that model that are implemented in the e200z3 and e200z335 core. This chapter identifies features defined by Book E, the Freescale Book E implementation standards (EIS), and the e200z3 implementation.
Page 190 (visibly) executed. An imprecise interrupt does not have this guarantee. • Book E defines critical and non-critical interrupt types, and the e200z3 defines an implementation-specific debug APU that includes the debug interrupt type. Each interrupt type provides separate resources (save/restore registers and return from interrupt instructions) that allow interrupts of one type to not interfere with the state handling of an interrupt of another type.
Page 191 Section 4.6, “Interrupt Definitions.” Table 4-2 lists interrupts implemented in the e200z3 and the exception conditions that cause them. Note that although this table lists system reset, Book E does not define system reset as an interrupt and assigns no interrupt vector to it.
Page 192 Section 4.6.20, “SPE Floating-Point Round Interrupt (IVOR34).” 4.6.20/4-27 Vector to [p_rstbase[0:19]] || 0xFFC in e200z3. Vector to [p_rstbase[0:29]] || 2’b00 in e200z335. Autovectored external and critical input interrupts use this IVOR. Vectored interrupts supply an interrupt vector offset directly. Exception Syndrome Register (ESR)
Page 193 Misaligned instruction fetch Instruction storage, instruction TLB External termination error (precise) Data storage, instruction storage When optional cache is present. Unused on e200z3 and e200z335. Machine State Register (MSR) The MSR, shown in Figure 4-4, defines the state of the processor.
Page 194 — Reserved, should be cleared. Wait state (power management) enable. Defined as optional by Book E and implemented in the e200z3. 0 Power management is disabled. 1 Power management is enabled. The processor can enter a power-saving mode when additional conditions are present.
Page 195 Table 4-5. MCSR Field Descriptions Bits Name Description Recoverable Machine check input pin Maybe — Reserved, should be cleared. — CP_PERR Cache push parity error Unlikely CPERR Cache parity error Precise e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 196 The value in the vector offset field of the IVOR assigned to the interrupt type is concatenated with the value in IVPR to form an instruction address at which execution is to begin. The e200z3 also defines the low-order bits of the IVORs (defined as zeros in Book E) as a context selector field to be used as the e200z3 Power Architecture Core Reference Manual, Rev.
Page 197 IVOR2 Data storage IVOR3 Instruction storage IVOR4 External input IVOR5 Alignment IVOR6 Program IVOR7 Floating-point unavailable IVOR8 System call IVOR9 Auxiliary processor unavailable. Not used by the e200z3. IVOR10 Decrementer e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 198 A critical input exception is signaled to the processor by the assertion of the critical interrupt pin (p_critint_b). When the e200z3 detects the exception, if critical interrupts are enabled (MSR[CE] = 1), the e200z3 takes the critical input interrupt. The p_critint_b input is a level-sensitive signal expected to remain asserted until the e200z3 acknowledges the interrupt.
Page 199 4.6.2 Machine Check Interrupt (IVOR1) The e200z3 implements the machine check exception as defined in Book E except for automatic clearing of MSR[DE]. The e200z3 initiates a machine check interrupt if MSR[ME]=1 and any of the machine check sources listed in Table 4-2 is detected.
Page 200 Register Setting Description CSRR0 On a best-effort basis, the e200z3 sets this to the address of some instruction that was executing or about to be executing when the machine check condition occurred. CSRR1 Set to the contents of the MSR at the time of the interrupt...
Page 201 CPU is in checkstop state. When a debug request is presented to the e200z3 core while it is in checkstop state, p_wakeup is asserted, and when m_clk is provided to the core, it temporarily exits checkstop state and enters debug mode. The p_chkstop output is negated while the core remains in a debug session (p_debug_b asserted).
Page 202 • Misaligned instruction fetch exceptions • The extension of the byte ordering exception cases. Exception extensions implemented in e200z3 for VLE involve extending the definition of the instruction storage interrupt to include the following: • Byte-ordering exceptions for instruction accesses •...
Page 203 (p_extint_b), a level-sensitive signal expected to remain asserted until the e200z3 acknowledges the external interrupt. If p_extint_b is negated early, recognition of the interrupt request is not guaranteed. When the e200z3 detects the exception, if the exception is enabled by MSR[EE], the e200z3 takes an external input interrupt.
Page 204 IVPR[32–47] || IVOR5[48–59] || 0b0000 4.6.7 Program Interrupt (IVOR6) The e200z3 implements the program interrupt as defined by Book E. A program interrupt occurs when no higher priority exception exists and one or more of the following exception conditions defined in Book E occur: •...
Page 205 SPRN value with SPRN[5] = 1 (even if the SPR is undefined). The e200z3 invokes a trap exception on execution of tw and twi if the trap conditions are met and the exception is not also enabled as a debug interrupt.
Page 206 System Call Interrupt (IVOR8) A system call interrupt occurs when a system call (sc, se_sc) is executed and no higher priority exception exists. Exception extensions implemented in e200z3 for VLE include modification of the system call interrupt definition to include updating the ESR.
Page 207 4.6.12 Fixed-Interval Timer Interrupt (IVOR11) The e200z3 implements the fixed-interval timer exception as defined in Book E. The triggering of the exception is caused by selected bits in the time base register changing from 0 to 1. A fixed-interval timer interrupt occurs when no higher priority exception exists, a fixed-interval timer exception exists (TSR[FIS]=1), and the interrupt is enabled (both TCR[FIE] and MSR[EE]=1).
Page 208 4.6.13 Watchdog Timer Interrupt (IVOR12) The e200z3 implements the watchdog timer interrupt as defined in Book E. The exception is triggered by the first enabled watchdog timeout. A watchdog timer interrupt occurs when no higher priority exception exists, a watchdog timer exception exists (TSR[WIS]=1), and the interrupt is enabled (both TCR[WIE] and MSR[CE] = 1).
Page 209 Set to the contents of the MSR at the time of the interrupt UCLE 0 — SPE 0 FE1 0 — — FE0 0 — [MIF] All other bits cleared. MCSR Unchanged DEAR Unchanged Vector IVPR[32–47] || IVOR14[48–59] || 0b0000 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 4-21...
Page 210 The e200z3 does not implement the data value compare debug mode, specified in Book E. The e200z3 implementation provides IAC linked with DAC exceptions. This results in a DAC exception only if one or more IAC conditions are also met.
Page 211 A critical interrupt context switch is detected. This exception is imprecise and unordered with respect to interrupt taken program flow. Note that a CIRPT debug interrupt occurs only when detecting a critical interrupt on the e200z3. (CIRPT) The address of the critical interrupt handler is saved in CSRR0/DSRR0. To avoid corrupting CSRR0 and CSRR1, critical interrupt taken debug events should not normally be enabled unless the debug APU is enabled.
Page 212 {DAC1R, DAC1W, DAC2R, DAC2W} Return debug event: Critical return debug event: CRET Debug counter event: {DCNT1, DCNT2} External debug event: {DEVT1, DEVT2} (optional) Imprecise debug event flag {IDE} Unchanged MCSR Unchanged e200z3 Power Architecture Core Reference Manual, Rev. 2 4-24 Freescale Semiconductor...
Page 213 When a reset request occurs, the processor branches to the system reset exception vector (value on p_rstbase[0:19] concatenated with 0xFFC in e200z3 and p_rstbase[0:29]concatenated with 2’b00 in e200z335 ) without attempting to reach a recoverable state. If reset occurs during normal operation, all operations stop and machine state is lost.
Page 214 Table 4-29. SPE Unavailable Interrupt Register Settings Register Setting Description SRR0 Set to the effective address of the excepting SPE instruction SRR1 Set to the contents of the MSR at the time of the interrupt e200z3 Power Architecture Core Reference Manual, Rev. 2 4-26 Freescale Semiconductor...
Page 215 The SPE floating-point round interrupt is taken when an SPE floating-point instruction generates an inexact result and inexact exceptions are enabled. Table 4-31 lists register settings when an SPE floating-point round interrupt is taken. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 4-27...
Page 216 IVPR[32–47] || IVOR34[48–59] || 0b0000 Exception Recognition and Priorities The following list of exception categories describes how the e200z3 handles exceptions up to the point of signaling the appropriate interrupt to occur. Also, instruction completion is defined as updating all architectural registers associated with that instruction as necessary, and then removing the instruction from the pipeline.
Page 217 Assertion of p_mcp_b , exception on fetch of first instruction of an interrupt handler, bus error on buffered store , bus error (XTE) with MSR[EE]=0 and current MSR[ME]=1, or assertion of p_nmi_b — — — e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 4-29...
Page 218 3. Debug: RET 3. Attempted execution of a rfi instruction 4. Debug: CRET 4. Attempted execution of an rfci instruction Note: Exceptions require corresponding debug event enabled, MSR[DE]=1, and DBCR0[IDM]=1. e200z3 Power Architecture Core Reference Manual, Rev. 2 4-30 Freescale Semiconductor...
Page 219 DAC or linked DAC/IAC on a load or store class instruction, the debug interrupt takes priority, and the saved PC value points to the load or store class instruction, rather than to the next instruction. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 220 MSR bits are unimplemented and are read as 0. Table 4-33. MSR Setting Due to Interrupt Bits MSR Definition Reset Setting Non-Critical Interrupt Critical Interrupt Debug Interrupt UCLE — —/0 —/0 — — — e200z3 Power Architecture Core Reference Manual, Rev. 2 4-32 Freescale Semiconductor...
Page 221 (rfdi) instructions perform context synchronization by allowing instructions issued earlier to complete before returning to the interrupted process. In general, execution of rfi, rfci, or rfdi ensures the following: e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 4-33...
Page 222 • stwcx. clears any outstanding reservations, ensuring that a load and reserve instruction in an old process is not paired with a store conditional instruction in a new one. e200z3 Power Architecture Core Reference Manual, Rev. 2 4-34 Freescale Semiconductor...
Page 223 5.1.2 TLB Entry Maintenance Features Summary The TLB entries of the e200z3 core complex must be loaded and maintained by the system software; this includes performing any required table search operations in memory. The e200z3 provides support for maintaining TLB entries in software with the resources shown in Table 5-1.
Page 224 4 Kbytes, the 12 lsbs always index within the page and are untranslated. e200z3 Power Architecture Core Reference Manual, Rev. 2...
Page 225 32-Entry Fully-Assoc. VSP Array (TLB1) 15–20 Bits* >12 Bits* 32-Bit Real Address Real Page Number Byte Address * Number of bits depends on page size (4 Kbytes–128 Mbytes) Figure 5-1. Effective-to-Real Address Translation Flow e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 226 This PID value is included as part of the virtual address in the translation process (PID0). For the e200z3 MMU, the PID is 8 bits in length. The most significant 24 bits are unimplemented and read as 0. The p_pid0[0:7] interface signals indicate the current process ID.
Page 227 Table 5-2. On a TLB hit, the corresponding bits of the real page number (RPN) field are used to form the real address. Table 5-2. Page Size (for e200z3 Core) and EPN Field Comparison Page Size EA to EPN Comparison...
Page 228 Memory Management Unit Table 5-2. Page Size (for e200z3 Core) and EPN Field Comparison (continued) Page Size EA to EPN Comparison SIZE Field SIZE (Bits 32–53; 2 × SIZE) Kbytes) 0b0111 16 Mbytes EA[32–39] = EPN[32–39]? 0b1000 64 Mbytes EA[32–37] = EPN[32–37]?
Page 229 TLB with fixed page sizes, TLB1 is used for a fully-associative TLB with variable page sizes, and TLB2 is arbitrarily defined by an implementation. The e200z3 MMU supports a single TLB that is fully associative and supports variable page sizes; thus it corresponds to TLB1 in the programming model.
Page 230 MAS0[ESEL] field before executing a tlbwe instruction. Alternately, the software can load the entry number of the next desired victim into MAS0[NV]. The e200z3 then automatically loads MAS0[ESEL] from MAS0[NV] on a TLB error condition as shown in Figure 5-5.
Page 231 Proper operation always occurs to guarded storage. 5.3.4 TLB Entry Field Summary Table 5-3 summarizes the fields of e200z3 TLB entries. Note that all of these fields are defined at the Freescale Book E level. Table 5-3. TLB Entry Bit Fields for e200z3 Field...
Page 232 Memory Management Unit Table 5-3. TLB Entry Bit Fields for e200z3 (continued) Field Description SIZE[0–3] Encoded page size 0000 Reserved 0001 4 Kbytes 0010 16 Kbytes 0011 64 Kbytes 0100 256 Kbytes 0101 1 Mbyte 0110 4 Mbytes 0111 16 Mbytes...
Page 233 (IPROT = 1) 30–31 Reserved These bits should be zero for future compatibility. They are ignored. • TLB Synchronize (tlbsync)—Treated as a privileged no-op by the e200z3. TLB Operations This section describes how the software (with some hardware assistance) maintains TLB1. 5.5.1 Translation Reload The TLB reload function is performed in software with some hardware assistance.
Page 234 5.5.5 TLB Coherency Control The e200z3 core provides the ability to invalidate a TLB entry as described in the Book E PowerPC architecture. The tlbivax instruction invalidates local TLB entries only. No broadcast is performed, as no hardware-based coherency support is provided.
Page 235 Section 2.16.4, “MMU Assist Registers (MAS0–MAS4, MAS6).” 5.6.1 MMU Configuration Register (MMUCFG) MMUCFG provides configuration information for the MMU supplied with this version of the e200z3 CPU core. See Section 2.16.2, “MMU Configuration Register (MMUCFG).” e200z3 Power Architecture Core Reference Manual, Rev. 2...
Page 236 MMU Assist Registers (MAS) The e200z3 uses MAS0–MAS4 and MAS6 SPRs to facilitate reading, writing, and searching the TLBs. The e200z3 does not implement MAS5, because the tlbsx instruction only searches based on a single SPID value. MAS registers are described in Section 2.16.4, “MMU Assist Registers (MAS0–MAS4, MAS6).”...
Page 237 MMU may be left enabled in the OnCE OCR, and normal translation (including the possibility of a TLB miss or DSI) remains in effect. Refer to Section 9.5.5.3, “OnCE Control Register (OCR),” for details on controlling MMU operation during debug sessions. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 5-15...
Page 238 Memory Management Unit e200z3 Power Architecture Core Reference Manual, Rev. 2 5-16 Freescale Semiconductor...
Page 239 Overview of Operation Figure 6-1 shows a block diagram of the e200z3 core. The instruction fetch unit prefetches instructions from memory into the instruction buffers. The decode unit decodes each instruction and generates information needed by the branch and execution units. Branch target instructions are written into the branch target prefetch buffers;...
Page 240 The instruction unit controls the flow of instructions to the instruction buffers and decode unit. Six prefetch buffers allow the instruction unit to fetch instructions ahead of actual execution, and serve to decouple memory and the execution pipeline. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 241 The load/store unit executes instructions that move data between the GPRs and the memory subsystem. A load followed by a dependent instruction does not incur any pipeline stall, except when the dependent e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 242 The fetch pipeline stages retrieve instructions from the memory system and determine where the next instruction fetch is performed. Up to two instructions every cycle are sent from memory to the instruction buffers. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 243 6.3.2 Instruction Buffers The e200z3 contains a set of instruction buffers that supply instructions into the instruction register (IR) for decoding. Instruction prefetches request a 64-bit double word and the buffer is filled with a pair of instructions at a time, except for the case of a change of flow fetch where the target is to the second (odd) word.
Page 244 HID0[BPRED] controls whether prediction is made for forward or backward branches (or both). To resolve branch instructions and improve the accuracy of branch predictions, the e200z3 implements a dynamic branch prediction mechanism using an 8-entry branch target buffer (BTB), a fully associative address cache of branch target addresses.
Page 245 The counter saturates in the strongly taken states when the prediction is correct. The e200z3 does not implement the static branch prediction that is defined by the PowerPC architecture. The BO prediction bit in branch encodings is ignored.
Page 246 In this case, the second load does not depend on its previous load data for its EA calculation. Notice that the memory access of the first load instruction overlaps in time with the EA calculation of the second load instruction. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 247 BTB. The resulting branch timing reduces to a single clock when the target fetch is initiated early enough and the branch is taken. Figure 6-9 shows basic pipeline flow for branch instructions. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 248 Store Figure 6-12 shows an example of pipelining two non–data-dependent load or store instructions with a following data-dependent single-cycle instruction. While the first load or store begins accessing memory e200z3 Power Architecture Core Reference Manual, Rev. 2 6-10 Freescale Semiconductor...
Page 249 Figure 6-14. In addition, execution of subsequent instructions stalls until the mfspr and mtspr instructions complete. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 6-11...
Page 250 WB cycle. This same protocol applies to MMU management instructions (such as tlbre, tlbwe, etc.) as well as to the DCRs. e200z3 Power Architecture Core Reference Manual, Rev. 2 6-12 Freescale Semiconductor...
Page 251 The isync, mbar, msync, rfi, rfci, rfdi, and sc instructions are dispatch-serialized. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 6-13...
Page 252 IFETCH 1st Instruction of handler ec_excp_detected* update_esr* update_msr* oldpc_-> srr0 * oldmsr_-> srr1 * * - internal operations Figure 6-17. Interrupt Recognition and Handler Instruction Execution e200z3 Power Architecture Core Reference Manual, Rev. 2 6-14 Freescale Semiconductor...
Page 253 IFETCH First Instruction of Handler ec_excp_detected* update_esr* update_msr* oldpc_-> srr0 * oldmsr_-> srr1 * * Internal Operations Figure 6-18. Interrupt Recognition and Handler Instruction Execution—Load/Store in Progress e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 6-15...
Page 254 Load/store multiple instruction cycles are represented as a fixed number of cycles plus a variable number of cycles where ‘n’ is the number of words accessed by the instruction. Additionally, cycle times marked with an ampersand (&) require additional cycles due to serialization. e200z3 Power Architecture Core Reference Manual, Rev. 2 6-16 Freescale Semiconductor...
Page 255 Latency Serialization Comments addc[o][.] None adde[o][.] None addi, e_addi[.], e_add16i, e_add2i., se_addi None addic[.], e_addic[.] None addis, e_add2is None addme[o][.] None addze[o][.] None add[o][.], se_add None andc[.], se_andc None e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 6-17...
Page 256 The UISA defines li as a simplified, mnemonic for addi. e_rlw, e_rlwi None isel None isync, se_isync Refetch Plus additional synchronization time lbz, e_lbz, se_lbz None Aligned lbzu, e_lbzu None Aligned e200z3 Power Architecture Core Reference Manual, Rev. 2 6-18 Freescale Semiconductor...
Page 257 Completion Plus additional synchronization time mtspr, (debug, MMU), se_mtctr, se_mtlr Completion Plus additional synchronization time mtspr, (except, debug, MMU) None mulhwu[.] None mulhw[.] None mulli, e_mulli, e_mull2i None e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 6-19...
Page 258 None srawi[.], se_srawi None sraw[.], se_sraw None srw[.], se_srw, e_srwi, se_srwi None stb, e_stb, se_stb None Aligned stbu, e_stbu None Aligned stbux None Aligned stbx None Aligned e200z3 Power Architecture Core Reference Manual, Rev. 2 6-20 Freescale Semiconductor...
Page 259 A load or store class instruction that follows an SPE FPU instruction stalls until it can be ensured that no previous instruction can generate a floating-point exception. This determination is based on which floating-point exception enable bits are set (FINVE, FOVFE, FUNFE, FDBZE, and FINXE) and at what e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 6-21...
Page 260 Latency Throughput Comments brinc evabs evaddiw evaddw evand evandc evcmpeq evcmpgts evcmpgtu evcmplts evcmpltu evcntlsw evcntlzw eveqv evextsb evextsh evmergehi evmergehilo evmergelo evmergelohi evnand evneg evnor evor evorc evrlw e200z3 Power Architecture Core Reference Manual, Rev. 2 6-22 Freescale Semiconductor...
Page 261 Actual timing depends on alignment; the table indicates timing for aligned operands. Table 6-5. SPE Load and Store Instruction Timing Instruction Latency Throughput Comments evldd evlddx evldh evldhx evldw evldwx evlhhesplat evlhhesplatx evlhhossplat evlhhossplatx evlhhousplat evlhhousplatx evlwhe e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 6-23...
Page 262 6-6. The table is sorted by opcode. For the divide instructions, the number of stall cycles is (latency) for following instructions. Table 6-6. SPE Complex Integer Instruction Timing Instruction Latency Throughput Comments evaddsmiaaw evaddssiaaw evaddumiaaw evaddusiaaw e200z3 Power Architecture Core Reference Manual, Rev. 2 6-24 Freescale Semiconductor...
Page 263 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 6-25...
Page 264 Power Architecture Core Reference Manual, Rev. 2 6-26 Freescale Semiconductor...
Page 265 6.7.1.4 Vector Floating-Point APU Instruction Timing Timings for embedded vector single-precision floating-point instructions are shown in Table 6-4. The number of stall cycles for evfsdiv is (latency) cycles. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 6-27...
Page 266 6.7.1.5 SPE Scalar Floating-Point Instruction Timing Timings for embedded scalar single-precision floating-point APU instructions are shown in Table 6-8. The table is sorted by opcode. e200z3 Power Architecture Core Reference Manual, Rev. 2 6-28 Freescale Semiconductor...
Page 267 The placement (location and alignment) of operands in memory affects relative performance of memory accesses, and in some cases, affects it significantly. Table 6-9 indicates the effects for the e200z3 core. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 6-29...
Page 268 String Note: Optimal: One EA calculation occurs. Good: Multiple EA calculations occur, which may cause additional bus activities with multiple bus transfers. Poor: Alignment Interrupt occurs. e200z3 Power Architecture Core Reference Manual, Rev. 2 6-30 Freescale Semiconductor...
Page 269 Chapter 7 External Core Complex Interfaces This chapter describes the external interfaces of the e200z3 core complex. Signal descriptions as well as data transfer protocols are documented in the following subsections. Section 7.4, “Internal Signals,” describes a number of internal signals that are not directly accessible to users, but they are mentioned in various chapters in this manual and aid in understanding the behavior of the core.
Page 270 'nex_' denotes Nexus3 signals. NOTE The “_b” suffix denotes an active low signal. Signals without the active-low suffix are active high. Figure 7-1 groups core bus and control signals by function. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 271 Module jd_en_once OnCE Control * (OnCE/Debug) jd_debug_b m_clk Clock jd_watchpt[0:n] p_masterid[3:0] jd_mclk_on MasterID nex_masterid[3:0] Config Test Interface Note These signals are internal to the core. Figure 7-1. Core Signal Groups e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 272 Byte strobes p_d_hbstrb[7:0] p_ i_ hrdata[63:0], Read data bus p_d_hrdata[63:0] p_d_hwdata[63:0] — Write data bus p_ i_ hready, Transfer ready p_d_hready p_ i_ hresp[2:0], Transfer response p_d_hresp[2:0] Master ID Configuration Signals e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 273 Low-power doze mode of operation p_nap Low-power nap mode of operation p_sleep Low-power sleep mode of operation p_wakeup Indicates to external clock control module to enable clocks and exit from low-power mode e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 274 JTAG test data out to master controller or pad j_tdo_en Enables TDO output buffer j_tst_log_rst Test-logic-reset state of JTAG controller j_capture_ir Capture_IR state of JTAG controller j_update_ir Update_IR state of JTAG controller e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 275 When a power-up reset is achieved, the two resets can be asserted independently. A reset output signal, p_resetout_b, is also provided. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 276 These outputs provide the address for a bus transfer. According to the AHB definition, p_haddr31 is the msb and p_haddr0 is the lsb. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 277 If the p_[d,i]_htrans[1:0] encoding is not IDLE or BUSY, a transfer is being requested. p_[d,i]_hwrite O Write. Defines the data transfer direction for the current bus cycle. State Asserted—The current bus cycle is a write. Meaning Negated—The current bus cycle is a read. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 278 Byte lane addressing is shown big-endian (left to right) regardless of the core’s endian mode. The byte in memory corresponding e200z3 Power Architecture Core Reference Manual, Rev. 2 7-10...
Page 279 — — — — — Byte @011 0 1 1 — — — — — — — Byte @100 1 0 0 — — — — — — — e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-11...
Page 280 ‘A B C D E F G H’ to memory. The core breaks misaligned accesses that cross a double-word boundary into a pair of accesses. Double-word transfers are always double-word–aligned. e200z3 Power Architecture Core Reference Manual, Rev. 2 7-12 Freescale Semiconductor...
Page 281 — — — — — — — — — — — — — — B. E. Half @1101 1 1 0 1 — — — — — — — — — — — — — — e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-13...
Page 282 — — — — — — — — — — — — — — 1 0 0 0 — — — — — — — — — — — — — — e200z3 Power Architecture Core Reference Manual, Rev. 2 7-14 Freescale Semiconductor...
Page 283 — — — — — — — — — — — — L. E. Word @1100 1 1 0 0 — — — — — — — — — — — — e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-15...
Page 284 Timing Assertion—ERROR and XFAIL are required to be 2-cycle responses that must be signaled one cycle before assertion of p_[d,i]_hready and must remain unchanged during the cycle p_[d,i]_hready is asserted. The XFAIL response is signaled to the CPU using the p_xfail_b internal signal. e200z3 Power Architecture Core Reference Manual, Rev. 2 7-16 Freescale Semiconductor...
Page 285 Assertion of p_ipend does not mean that exception processing for the interrupt has begun. Negated—A p_extint_b or p_critint_b interrupt request or an enabled timer facility interrupt has not been recognized. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-17...
Page 286 It is internally qualified with this transition, but must remain asserted to be guaranteed to be recognized Table 7-12 describes the timer facility signals, which are associated with the time base, watchdog, fixed-interval, and decrementer facilities. e200z3 Power Architecture Core Reference Manual, Rev. 2 7-18 Freescale Semiconductor...
Page 287 Section 2.4.2, “Processor ID Register (PIR).” Timing Intended to remain in a static condition and are not internally synchronized. p_pid0[0:7] O PID0 outputs. Reflected to PID0[56–63]. See Section 2.16.5, “Process ID Register (PID0).” e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-19...
Page 288 1111100 Complete rfi, rfci, or rfdi 1111111 Complete se_rfi, se_rfci, or se_rfdi Timing Synchronous with m_clk , so the indicated status may not apply to a current bus transfer. e200z3 Power Architecture Core Reference Manual, Rev. 2 7-20 Freescale Semiconductor...
Page 289 O Processor stopped. The active-high p_stopped output signal indicates that the processor entered the stopped state. State Asserted—The processor is in stopped state. Meaning Negated—The processor is not in stopped state. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-21...
Page 290 Only a transition from negated to asserted state of p_ude causes an event to occur. However, the level on this signal causes assertion of p_wakeup . e200z3 Power Architecture Core Reference Manual, Rev. 2 7-22 Freescale Semiconductor...
Page 291 Table 7-18. Core Debug/Emulation Support Signals Signal Type Description jd_en_once Enable full OnCE operation jd_debug_b Debug session indicator jd_de_b Debug request jd_de_en DE_b active high output enable jd_mclk_on CPU clock is active indicator e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-23...
Page 292 O Watchpoint events. Indicate whether a watchpoint occurred. Each debug address compare function [0:7] (IAC1–IAC4, DAC1–DAC2), and debug counter event (DCNT1–DCNT2) is capable of triggering a watchpoint output. State Asserted—A watchpoint occurred Meaning Negated—No watchpoint occurred e200z3 Power Architecture Core Reference Manual, Rev. 2 7-24 Freescale Semiconductor...
Page 293 OnCE on the rising edge and is clocked out of the OnCE serial port on the rising edge). The debug serial clock frequency must not exceed 50% of the processor clock frequency. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 294 O Update IR. Indicates the TAP controller is in the Update_IR state. State Asserted—The TAP controller is in Update_IR state. Meaning Negated—The TAP controller is not in Update_IR state. e200z3 Power Architecture Core Reference Manual, Rev. 2 7-26 Freescale Semiconductor...
Page 295 Negated—No Nexus register is selected. j_lsrl_regsel O LSRL register select. State Asserted—A decode of OCMD[RS] indicates an external LSRL register is selected Meaning (0b1111101 encoding) for access using the core TAP controller. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-27...
Page 296 NOTES: clk_shfter = j_tclk & (j_shift_dr | j_capture_dr) clk_reg0 = j_tclk & j_update_gp_reg & j_gp_regsel[0] clk_reg1 = j_tclk & j_update_gp_reg & j_gp_regsel[1] Figure 7-2. Example External JTAG Register Design e200z3 Power Architecture Core Reference Manual, Rev. 2 7-28 Freescale Semiconductor...
Page 297 JTAG ID version. Corresponds to the 4-bit version number in the JTAG ID register. These inputs are normally static. They are provided to the customer for strapping to facilitate identification of component variants. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-29...
Page 298 A request cycle, where address and attributes are driven along with a transfer request • One or more memory access cycles to perform accesses and return data to the CPU for alignment, sign or zero extension, and forwarding. e200z3 Power Architecture Core Reference Manual, Rev. 2 7-30 Freescale Semiconductor...
Page 299 A bus error termination for any write access or read access that references data specifically requested by the execution unit causes the core to begin exception processing. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-31...
Page 300 Clock 3 (C3)—During C3, the addr memory access takes place, using the address and attribute values that were driven during C2 to enable reading of one or more bytes of memory. Read data e200z3 Power Architecture Core Reference Manual, Rev. 2 7-32 Freescale Semiconductor...
Page 301 Figure 7-4. Read with Wait-State, Single-Cycle Reads, Full Pipelining e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-33...
Page 302 Clock 3 (C3)—During C3, write data for addr is driven, and the addr memory access takes place using the address and attribute values (driven during C2) to enable writing of one or more bytes of e200z3 Power Architecture Core Reference Manual, Rev. 2 7-34 Freescale Semiconductor...
Page 303 The request for access to addr is taken at the end of C4, and during C5, the slave device provides a ready/OKAY response. In C5, no further accesses are requested. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-35...
Page 304 Figure 7-8 shows another sequence of read and write cycles. This example shows an interleaved write access between two reads. e200z3 Power Architecture Core Reference Manual, Rev. 2 7-36 Freescale Semiconductor...
Page 305 Figure 7-9 shows another sequence of read and write cycles. In this example, reads incur a single wait state. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-37...
Page 306 Figure 7-10 shows another sequence of read and write cycles. In this example, reads incur a single wait state. e200z3 Power Architecture Core Reference Manual, Rev. 2 7-38 Freescale Semiconductor...
Page 307 The read to addr is misaligned across a 64-bit boundary. Note that only half-word and word transfers may be misaligned; double-word transfers are always aligned. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-39...
Page 308 The write to addr is misaligned across a 64-bit boundary. Note that only half-word and word transfers may be misaligned; double-word transfers are always aligned. e200z3 Power Architecture Core Reference Manual, Rev. 2 7-40 Freescale Semiconductor...
Page 309 An example of a misaligned write cycle followed by an aligned read cycle is shown in Figure 7-13. It is similar to the example in Figure 7-12. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-41...
Page 310 Figure 7-13. Misaligned Write, Single Cycle Read Transfer, Full Pipelining e200z3 Power Architecture Core Reference Manual, Rev. 2 7-42 Freescale Semiconductor...
Page 311 NOTE Bursts can be interrupted immediately at any time and can be followed by any type of cycle. No idle cycle is required. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-43...
Page 312 Figure 7-15. Burst Read with Wait-state Transfer The first cycle of the burst incurs a single wait-state. e200z3 Power Architecture Core Reference Manual, Rev. 2 7-44 Freescale Semiconductor...
Page 313 Figure 7-16. Burst Write Transfer e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-45...
Page 314 Figure 7-17. Burst Write with Wait-State Transfer The first cycle of the burst incurs a single wait-state. Data for the second beat of the burst is valid the cycle after the second beat is taken. e200z3 Power Architecture Core Reference Manual, Rev. 2 7-46 Freescale Semiconductor...
Page 315 NOTE Bursts may be of any length (including a single beat) and may be followed immediately by any type of transfer. No idle cycles are required. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-47...
Page 316 Figure 7-19. Burst Read with Wait-State Transfer, Retraction The first cycle of the burst incurs a single wait state, and the burst is replaced by another burst. e200z3 Power Architecture Core Reference Manual, Rev. 2 7-48 Freescale Semiconductor...
Page 317 C4; during C5, the data and a ready/OKAY response is provided by the slave device. In cycle C5, no further accesses are requested. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-49...
Page 318 Figure 7-21. Read Transfer with Wait-State, Address Retraction e200z3 Power Architecture Core Reference Manual, Rev. 2 7-50 Freescale Semiconductor...
Page 319 The cycle that may have been previously pending while waiting for a response that terminates with error may be changed. It is not required to remain unchanged when an error response is received. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-51...
Page 320 The following figures outline cases where an error termination for a given cycle causes a pending request to be aborted prior to initiation. e200z3 Power Architecture Core Reference Manual, Rev. 2 7-52...
Page 321 C4 and is taken at the end of C4. During C5, read data is supplied for the addr read, and the access is terminated normally. In this example of error termination, a subsequent access was aborted. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-53...
Page 322 Figure 7-26 shows another example of error termination, this time on the initial portion of a burst read. The aborted burst is followed by a burst write. e200z3 Power Architecture Core Reference Manual, Rev. 2 7-54 Freescale Semiconductor...
Page 323 C4; during C5, the data and a ready/OKAY response are provided by the slave device. In cycle C5, no further accesses are requested. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-55...
Page 324 Figure 7-27. Read Transfer with Wait-State, Address Retraction e200z3 Power Architecture Core Reference Manual, Rev. 2 7-56 Freescale Semiconductor...
Page 325 , p_ude , OCR[WKUP] p_wakeup Figure 7-29. Wakeup Control Signal ( p_wakeup ) e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 7-57...
Page 326 Note that p_ipend is asserted combinationally from the p_extint_b and p_critint_b inputs. m_clk p_extint_b p_critint_b Exception vector fetch p_ipend Figure 7-31. Interrupt Pending Operation e200z3 Power Architecture Core Reference Manual, Rev. 2 7-58 Freescale Semiconductor...
Page 327 3 indicates that the values present at the rise of cycle 2 (vector ‘A’) have been committed to. During cycle 3, the CPU begins instruction fetching of the handler for vector ‘A’. The new e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 328 B handlr B hand + 8 cache access int B hand addr int B hand + 8 cache miss Figure 7-33. Interrupt Acknowledge Operation Case 2 e200z3 Power Architecture Core Reference Manual, Rev. 2 7-60 Freescale Semiconductor...
Page 329 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 330 (TSR[WIS] = 1 and TCR[WIE] = 1, or TSR[DIS] = 1 and TCR[DIE] = 1, or TSR[FIS] = 1 and TCR[FIE] = 1). May be used to exit low-power operation or for other system purposes. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 331 CPU remains in a debug session (jd_debug_b asserted). When the debug session is exited, the CPU resamples the p_halt and p_stop inputs and re-enters halted or stopped state as appropriate. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 332 Power Management e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 333 Debug Support Introduction This chapter describes the debug features of the e200z3 core, including the software and hardware debug facilities, events, and registers. It also details the external debug support features available and introduces the reader to the on-chip emulation circuitry (OnCE) and its key attributes, that is, the interface signals, debug inputs, and outputs.
Page 334 DBERC0. If the hardware debug facility is enabled, software is blocked from modifying the debug facilities. In addition, because resources are owned by the hardware debugger, inconsistent values may be present if software attempts to read debug-related resources. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 335 MSR values have been saved into DSRR0/1, and the new PC pointing to the debug interrupt handler, along with the new MSR updates. At this point, hardware priority takes over, and the CPU enters debug mode. Figure 9-1 shows the core debug resources. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 336 DBCR1 Debug control register 1 DBCR2 Debug control register 2 DBCR3 Debug control register 3 DBCR4 Debug control register 4 DVC1 Data value compare 1 DVC2 Data value compare 2 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 337 The following types of debug events are defined by Book E: • Instruction address compare debug events • Data address compare debug events • Trap debug events • Branch taken debug events e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 338 DSRR1 are used to store the address of the instruction following a load or store, assuming that the debug APU is enabled. If it is disabled, CSRR0 is used. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 339 • DAC events are not signaled on the following: —The second portion of a misaligned load or store that is broken up into two separate accesses —The tlbre, tlbwe, tlbsx, or tlbivax instructions e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 340 When a branch taken debug event is recognized, DBSR[BRT] is set to record the debug exception, and the address of the branch instruction is recorded in DSRR0 (only when the interrupt is taken). e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 341 DSRR0 holds the address of the critical interrupt handler. Note: To avoid corruption of CSRR0 or CSRR1, this debug event should not normally be enabled unless the debug APU is also enabled. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 342 When DBCR0[EDM] is set, debug events enabled to set respective DBSR status bits also cause the CPU to enter debug mode, as opposed to generating debug interrupts. In debug mode, e200z3 Power Architecture Core Reference Manual, Rev. 2 9-10...
Page 343 The core does not contain IEEE 1149.1 standard boundary cells on its interface, as it is a building block for further integration. It does not support the JTAG-related boundary scan e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 344 The OnCE logic provides for Nexus class 1 static debug capability (using the same set of resources available to software while the core is in internal debug mode), and is present in all e200z3-based designs. The OnCE module also provides support for directly integrating a Nexus class 2 or class 3 real-time debug unit with the core for development of real-time systems where traditional static debug is insufficient.
Page 345 Other resources are accessed in a similar manner. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 346 Enables TDO output buffer Set when the TAP controller is in the Shift-DR or Shift-IR state. A full description of JTAG signals is provided in Section 7.3.2, “JTAG ID Signals.” e200z3 Power Architecture Core Reference Manual, Rev. 2 9-14 Freescale Semiconductor...
Page 347 OnCE Interface Signals The following sections describe additional OnCE interface signals to other external blocks such as a Nexus controller and external blocks that may need information pertaining to debug operation. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 9-15...
Page 348 OnCE controller. See Section 9.5.5.2, “OnCE Command Register (OCMD),” for more information on the function of the GO and EX bits. This signal is not normally used by the CPU. e200z3 Power Architecture Core Reference Manual, Rev. 2 9-16 Freescale Semiconductor...
Page 349 Update-DR states. TCLK OnCE Command Register Update OnCE Decoder Status and Control Registers Mode Select Register Register Read Control/ Write Status Figure 9-4. OnCE Controller and Serial Interface e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 9-17...
Page 350 9-5. It is updated when the TAP controller enters the Update-IR state. It contains fields for controlling access to a resource, as well as controlling single-step operation and exit from OnCE mode. e200z3 Power Architecture Core Reference Manual, Rev. 2 9-18 Freescale Semiconductor...
Page 351 Debug firmware should mask these exceptions as appropriate. OSR[ERR] indicates such an occurrence. 0 Inactive (no action taken) 1 Execute instruction in IR e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 9-19...
Page 352 CPUSCR or no register selected. After executing a single instruction, the CPU re-enters debug mode and awaits further commands. During single-stepping, exception conditions may occur if not e200z3 Power Architecture Core Reference Manual, Rev. 2 9-20 Freescale Semiconductor...
Page 353 Reserved, should be cleared. I_DE Instruction side debug TLB E attribute bit. Provides the E attribute bit for instruction accesses when the MMU is disabled for instruction accesses during a debug session. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 9-21...
Page 354 NOTE A scan operation to update the CPUSCR is required before exiting debug mode. e200z3 Power Architecture Core Reference Manual, Rev. 2 9-22 Freescale Semiconductor...
Page 355 Reads of DBSR while the CPU is running may not give data that is self-consistent due to synchronization across clock domains. IAC1 IAC2 IAC3 IAC4 JTAG ID — — Read only e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 9-23...
Page 356 The OSR indicates that the CPU has entered the debug mode through the debug status bit. The following sections describe how debug mode is entered assuming the OnCE circuitry has been enabled. OnCE operation is enabled by the assertion of the jd_en_once input (see Table 9-2). e200z3 Power Architecture Core Reference Manual, Rev. 2 9-24 Freescale Semiconductor...
Page 357 CPUSCR. Once debug mode has been entered, it is required to scan in and update this register before exiting debug mode. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 9-25...
Page 358 This register is affected by the operations performed during the debug session and should normally be restored by the external command controller when returning to e200z3 Power Architecture Core Reference Manual, Rev. 2 9-26...
Page 359 Debug firmware should initialize the PC and IR values in the CPUSCR with desired values before exiting debug mode if this bit was set when debug mode was initially entered. 0 No error condition exists. 1 Error condition exists. PC and IR are corrupted. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 9-27...
Page 360 CTL register should be written with the FFRA bit set as appropriate and all other bits cleared, and with IR set to the value of the desired instruction to be executed. e200z3 Power Architecture Core Reference Manual, Rev. 2 9-28...
Page 361 The control state register FFRA bit forces the value of the WBBR to be lower e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 9-29...
Page 362 FIFO register. The registers are serially available to the external command controller through the common FIFO address. Figure 9-10 shows the block diagram of the PC FIFO. e200z3 Power Architecture Core Reference Manual, Rev. 2 9-30 Freescale Semiconductor...
Page 363 CPU into debug mode. After completing all accesses to the PC FIFO, another OCMD value that does not select the PC FIFO should be entered to allow the PC FIFO to resume updating. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 364 IAC4 compares are enabled to set DBSR status. jd_watchpt[4] DAC1 Data address compare 1 watchpoint. Set whenever a DAC1 compare occurs regardless of whether DAC1 compares are enabled to set DBSR status. e200z3 Power Architecture Core Reference Manual, Rev. 2 9-32 Freescale Semiconductor...
Page 365 Shift-IR state. The CPUSCR is shifted out during the Shift-DR state. The debugger should save the scanned-out value of CPUSCR for later restoration. 4. Select the DBCR0 register and update it with DBCR0[EDM] set. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 9-33...
Page 366 (CTL)”) with a Go+Exit OnCE command value. 7. OCR[WKUP] may then be cleared. NOTE These steps are meant by way of examples rather than as an exact template for debugger operation. e200z3 Power Architecture Core Reference Manual, Rev. 2 9-34 Freescale Semiconductor...
Page 367 Chapter 10 Nexus3/Nexus2+ Module The e200z3 Nexus3 module provides real-time development capabilities for e200z3 processors in compliance with the IEEE-ISTO Nexus 5001-2003 standard. This module provides development support capabilities without requiring the use of address and data pins for internal visibility. Note that the e200z335 supports Nexus 2+ with additional Class 3 and Class 4 features available.
Page 368 JTAG data register (DR) scan. Nexus1 The e200z3 (OnCE) debug module. This module integrated with each e200z3 processor provides all static, core-halted, debug functionality. This module complies with class 1 of the IEEE-ISTO 5001 standard.
Page 369 The configuration of the message start/end out pins, 1 or 2, is determined at the SOC integration level. This option is hard-wired based on SOC bandwidth requirements. Figure 10-1 Figure 10-2 shows the functional block diagram. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 10-3...
Page 370 Note: The nex_aux_req[1:0] , npc_aux_grant , and nex_aux_busy signals are used for inter-module communication in a multiple Nexus environment. They are not pins on the SoC. Figure 10-1. Nexus3 Functional Block Diagram e200z3 Power Architecture Core Reference Manual, Rev. 2 10-4 Freescale Semiconductor...
Page 371 The Nexus module is enabled by loading a single instruction, NEXUS3-Access, into the JTAG instruction register/OnCE OCMD register. For the e200z3 Nexus3 module, the OCMD value is 0b00_0111_1100. Once enabled, the module is ready to accept control input through the JTAG/OnCE pins.
Page 372 Source processor identifier (multiple Nexus configuration) Fixed Data size. Refer to Table 10-6. Variable Unique portion of the data write address Variable Data write value(s). See data trace section for details. e200z3 Power Architecture Core Reference Manual, Rev. 2 10-6 Freescale Semiconductor...
Page 373 Variable Data read value(s). See data trace section for details. Watchpoint message Fixed TCODE number = 15 (0x0F) Fixed Source processor identifier (multiple Nexus configuration) Fixed Number indicating watchpoint source(s) e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 10-7...
Page 374 Nexus3/Nexus2+ error message. Table 10-3. Error Code Encodings (TCODE = 8) Error Code Description (ECODE) 00000 Ownership trace overrun 00001 Program trace overrun e200z3 Power Architecture Core Reference Manual, Rev. 2 10-8 Freescale Semiconductor...
Page 375 Table 10-6. Data Trace Size Encodings (TCODE = 5, 6, 13, or 14) DTM Size Encoding Transfer Size Byte Half-word (2 bytes) e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 10-9...
Page 376 0x07 Development status (DS) 0x08 — Read/write access control/status (RWCS) 0x0E 0x0F Read/write access address (RWA) 0x12 0x13 Read/write access data (RWD) 0x14 0x15 Watchpoint trigger (WT) 0x16 0x17 e200z3 Power Architecture Core Reference Manual, Rev. 2 10-10 Freescale Semiconductor...
Page 377 Nexus3/Nexus2+, but the PCR is shown here for reference only. 2 PCR_INDEX is a parameter determined by the SoC. Refer to the reference manual for the device integrating the e200z3 core for more information on how this parameter is implemented for each Nexus module.
Page 378 The CSC and PCR registers exist in a separate module at the SoC level in a multiple Nexus environment. If the e200z3 Nexus3/Nexus2+ module is the only Nexus module, these registers are not implemented and the e200z3 Nexus3/Nexus2+-defined development control register 1 (DC1) is used to control Nexus port functionality.
Page 379 Watchpoint trace enable 0 Watchpoint messaging disabled 1 Watchpoint messaging enabled 23–8 — Reserved 7–5 Overrun control Generate overrun messages 001–010 Reserved Delay processor for BTM/DTM/OTM overruns 1XX Reserved e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 10-13...
Page 380 #7 (DCNT2 from Nexus1) triggers nex_evto_b 23–0 — Reserved NOTE The EOC bits in DC1 must be programmed to trigger EVTO on watchpoint occurrence for the EWC bits to have any effect. e200z3 Power Architecture Core Reference Manual, Rev. 2 10-14 Freescale Semiconductor...
Page 381 When debug mode is entered or exited, or an SOC- or e200z3-defined low-power mode is entered, a debug status message is transmitted with DS[31–25]. The external tool can read this register at any time.
Page 382 Write access completed without error Read access error has occurred. Write access error has occurred Read access completed without error Write access has not completed Not allowed Not allowed e200z3 Power Architecture Core Reference Manual, Rev. 2 10-16 Freescale Semiconductor...
Page 383 First RWD pass (low order data) Second RWD pass (high order data) Note: "X" indicates byte lanes with valid data “—” indicates byte lanes which will contain unused data. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 10-17...
Page 384 10-10, provides the system bus address to be accessed when initiating a read or a write access. Field Read/Write Data Reset All zeros Read/Write Number Figure 10-10. Read/Write Access Address Register (RWA) e200z3 Power Architecture Core Reference Manual, Rev. 2 10-18 Freescale Semiconductor...
Page 385 The watchpoint trigger register, shown in Figure 10-11, allows the watchpoints defined within the e200z3 Nexus1 logic to trigger actions. These watchpoints can control program and/or data trace enable and disable. The WT bits can be used to produce an address related window for triggering trace messages.
Page 386 1X Enable data write trace 29–28 RWT2 Read/write trace 2 00 No trace enabled X1 Enable data read trace 1X Enable data write trace 27–8 — Reserved, should be cleared. e200z3 Power Architecture Core Reference Manual, Rev. 2 10-20 Freescale Semiconductor...
Page 387 Figure 10-14. Data Trace End Address Registers 1 and 2 (DTEA n ) Table 10-19 shows the range that is selected for data trace for various cases of DTSA being less than, greater than, or equal to DTEA. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 10-21...
Page 388 Figure 10-15. Nexus3/Nexus2+ Register Access through JTAG/OnCE (Example) Table 10-20. Nexus Register Example Field Description Nexus Register Index Selected from values in Table 10-7 Read/write (R/W) 0 Read 1 Write e200z3 Power Architecture Core Reference Manual, Rev. 2 10-22 Freescale Semiconductor...
Page 389 There are two conditions that cause an ownership trace message: 1. When new information is updated in the OTR register or process ID register by the e200z3 processor, the data is latched within Nexus and is messaged out through the auxiliary port, allowing development tools to trace ownership flow.
Page 390 Nexus. • Writes to the e200z3 internal process ID register will pulse a write signal to Nexus. The data value written into the process ID register is latched and formed into the ownership trace message that is queued to be transmitted.
Page 391 Program trace is implemented using branch trace messaging (BTM) as required by the class 3 IEEE-ISTO 5001-2003 standard definition. Branch trace messaging for e200z3 processors is accomplished by snooping the e200z3 virtual address bus, between the CPU and MMU, attribute signals, and CPU status p_pstat[0:5].
Page 392 10.7.2 BTM Message Formats The e200z3 Nexus3/Nexus2+ block supports three types of traditional BTM messages: direct, indirect, and synchronized messages. It supports two types of branch history BTM messages: indirect branch history, and indirect branch history with synchronized messages. Debug status messages and error messages are also supported.
Page 393 (RDATA) field. This history information can be concatenated by the development tool with the e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 394 When the CPU enters debug mode, a PCM is generated. The instruction count and history information provided by the PCM can be used to determine the last sequence of instructions executed prior to debug mode entry. e200z3 Power Architecture Core Reference Manual, Rev. 2 10-28 Freescale Semiconductor...
Page 395 00111. If a watchpoint also attempts to be queued while the FIFO is being emptied, the error message incorporates error encoding 01000. NOTE DC1[OVC] can be set to delay the CPU in order to alleviate, but not eliminate, potential overrun situations. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 10-29...
Page 396 Full Target Address Sequence Count Source Process TOCODE (001011 or 001100) Maximum length = 50 bits; minimum length = 12 bits Figure 10-25. Direct/Indirect Branch with Synchronization Message Format e200z3 Power Architecture Core Reference Manual, Rev. 2 10-30 Freescale Semiconductor...
Page 397 Whenever the CPU switches execution mode into or out of a sequence of VLE instructions, the next switch branch trace message will be a Direct/Indirect Branch w/ Sync Message. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 10-31...
Page 398 Both types of branch trace messaging can be enabled in one of two ways: • Setting DC1[TM] to enable program trace • Using WT[PTS] to enable program trace on watchpoint hits. e200z3 watchpoints are configured within the CPU. 10.7.3.2 Relative Addressing The relative address feature is compliant with the IEEE-ISTO 5001-2003 standard recommendations and is designed to reduce the number of bits transmitted for addresses of indirect branch messages.
Page 399 NOTE If multiple trace messages need to be queued at the same time, watchpoint messages have the highest priority: (WPM → OTM → BTM → DTM). e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 10-33...
Page 400 Source processor = 0000 Source processor = 0000 Number of sequential instructions = 3 Error code = 1 (Queue overrun—BTM only) Figure 10-30. Program Trace—Direct Branch (Traditional) and Error Messages e200z3 Power Architecture Core Reference Manual, Rev. 2 10-34 Freescale Semiconductor...
Page 401 10.8.1 Data Trace Messaging (DTM) Data trace messaging for the e200z3 is accomplished by snooping the e200z3 virtual data bus between the CPU and MMU, and storing the information for qualifying access, based on enabled features and matching target addresses. The Nexus3/Nexus2+ module traces all data accesses that meet the selected range and attributes.
Page 402 Maximum length = 109 bits; minimum length = 15 bits Figure 10-33. Data Read Message Format NOTE For e200z3-based CPUs, the double-word encoding, p_tsiz = 0, indicates a double-word access and is sent out as a single data trace message with a single 64-bit data value.
Page 403 Source TCODE Data Value Full Address Size Process (001101 or 001110) Maximum length = 109 bit; Minimum length = 15 bits Figure 10-35. Data Write/Read with Synchronization Message Format e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 10-37...
Page 404 If multiple trace messages need to be queued simultaneously, watchpoint messages have the highest priority: WPM → OTM → BTM → DTM. Up to two messages may be simultaneously queued. e200z3 Power Architecture Core Reference Manual, Rev. 2 10-38 Freescale Semiconductor...
Page 405 DTM channel. Data trace windowing is achieved through the address range defined by the DTEA and DTSA registers and by DTC[RC1n]. All e200z3-initiated read/write accesses that fall inside or outside these address ranges, as programmed, are candidates to be traced.
Page 406 MSEO_B[1:0] MDO[7:0] 00001000 00001000 xxxxxxxx TCODE = 8 Source processor = 0000 Error code = 2 (queue overrun - DTM only) Figure 10-38. Error Message (Data Trace Only Encoded) e200z3 Power Architecture Core Reference Manual, Rev. 2 10-40 Freescale Semiconductor...
Page 407 This message includes the watchpoint number indicating which watchpoint caused the message. The occurrence of any of the e200z3-defined watchpoints can be programmed to assert the event out, nex_evto_b, pin for one period of the output clock, nex_mcko; see Table 10-31 for details on nex_evto_b.
Page 408 TCODE = 8 Source processor = 00 Source processor = 00 Watchpoint number = 2 Error code = 6 (Queue overrun—WPM only) Figure 10-41. Watchpoint Message and Watchpoint Error Message e200z3 Power Architecture Core Reference Manual, Rev. 2 10-42 Freescale Semiconductor...
Page 409 The read/write access feature allows access to memory-mapped resources through the JTAG/OnCE port. The read/write mechanism supports single as well as block reads and writes to e200z3 AHB resources. The Nexus3/Nexus2+ module is capable of accessing resources on the e200z3 system bus, AHB, with multiple configurable priority levels.
Page 410 5. When the entire burst transfer has completed without error (ERR=0), Nexus3/Nexus2+ then asserts the nex_rdy_b pin, and RWCS[DV] is cleared to indicate the end of the block write access. e200z3 Power Architecture Core Reference Manual, Rev. 2 10-44 Freescale Semiconductor...
Page 411 Nexus register index of 0xA; Table 10-7. NOTE Only the nex_rdy_b signal and the DV and ERR bits within RWCS provide read/write access status to the external development tool. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 10-45...
Page 412 The actual RWA and CNT values within RWCS are not changed when executing a block read access, burst or non-burst. The original values can be read by the external development tool at any time. e200z3 Power Architecture Core Reference Manual, Rev. 2 10-46 Freescale Semiconductor...
Page 413 The Nexus3/Nexus2+ module handles various error conditions as described in the following sections. 10.10.7.1 AHB Read/Write Error All address and data errors that occur on read/write accesses to the e200z3 AHB system bus return a transfer error encoding on the p_hresp[1:0] signals. If this occurs, the following steps are taken: 1.
Page 414 All Nexus3/Nexus2+ input functionality is controlled through the JTAG/OnCE port, in compliance with IEEE 1149.1. (See Section 10.5, “Nexus3/Nexus2+ Register Access Through JTAG/OnCE,” for details.) The JTAG pins are incorporated as I/O to the e200z3 processor and are further described in Section 9.5.2, “JTAG/OnCE Signals.” Table 10-30. JTAG Pins for Nexus3/Nexus2+...
Page 415 • Program trace and data trace synchronization messages (provided program trace and data trace are enabled and EIC = 00). • Debug request to e200z3 Nexus1 module (provided EIC = 01 and this feature is implemented). The Nexus auxiliary port arbitration pins are used when the Nexus3/Nexus2+ module is implemented in a multiple Nexus SoC that shares a single auxiliary output port.
Page 416 2x the number of nex_mdo[n:0] pins. This ensures that a false end-of-message state is not entered by emitting two consecutive 1s on nex_mseo_b before the actual end of message. e200z3 Power Architecture Core Reference Manual, Rev. 2 10-50...
Page 417 This can be an advantage when small, variable sized packets are transferred. NOTE The end message state may also indicate the end of a variable-length packet as well as the end of the message when using the dual-pin option. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 10-51...
Page 418 Nexus3/Nexus2+ Module 10.12 Rules for Output Messages e200z3-based class 3–compliant embedded processors must provide messages through the auxiliary port in a consistent manner as described below: • A variable-length packet within a message must end on a port boundary. •...
Page 419 T0 and S0 are the least significant bits, where Tx = TCODE number (fixed); Sx = Source processor (fixed); Ix = Number of instructions (variable); Ax = Unique portion of the address (variable). e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 420 T0, A0, D0 are the least-significant bits, where Tx = TCODE number (fixed); Sx = Source processor (fixed); Zx = Data size (fixed); Ax = Unique portion of the address (variable); Dx = Write data (variable-8, 16 or 32-bit). e200z3 Power Architecture Core Reference Manual, Rev. 2 10-54...
Page 421 (31) TCK clocks issued to transfer register value to TDO pin while shifting in TDI value SHIFT-DR—EXIT1–DR (MSB of value is shifted in/out of shifter) EXIT1-DR—UPDATE–DR (if access is write, shifter is transferred to register) UPDATE-DR—RUN-TEST/IDLE (transfer complete–Nexus controller to register select state) e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor 10-55...
Page 422 Nexus command = read read/write access data register (RWD) Write RWD (data output on TDO) — Wait for falling edge of nex_rdy_b pin — If CNT > 0, go back to Step #5 e200z3 Power Architecture Core Reference Manual, Rev. 2 10-56 Freescale Semiconductor...
Page 423 10.7.1.3, 10-25, before the last paragraph, added the sentence, “Branch history messaging facilitates program trace by providing the information described in Section 10.7.1.1, “e200z3 Indirect Branch Message Instructions (Book E).” 12/22/2005 Initial release. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 424 Revision History e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor...
Page 425 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor Glossary-1...
Page 426 Clean. An operation that causes a cache block to be written to memory, if modified, and then left in a valid, unmodified state in the cache. Clear. To cause a bit or bit field to register a value of zero. See also Set. e200z3 Power Architecture Core Reference Manual, Rev. 2 Glossary-2 Freescale Semiconductor...
Page 427 Flush. An operation that causes a cache block to be invalidated and the data, if modified, to be written to memory. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor Glossary-3...
Page 428 See Out-of-order. Instruction latency. The total number of clock cycles necessary to execute an instruction and make ready the results of that instruction. e200z3 Power Architecture Core Reference Manual, Rev. 2 Glossary-4 Freescale Semiconductor...
Page 429 (logical) address to a physical address, providing protection mechanisms, and defining caching methods. Most-significant bit (msb). The highest-order bit in an address, registers, data element, or instruction encoding. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor Glossary-5...
Page 430 PTEGs in the page table depends on the size of the page table (as specified in the SDR1 register). Physical memory. The actual memory that can be accessed through the system’s memory bus. e200z3 Power Architecture Core Reference Manual, Rev. 2 Glossary-6 Freescale Semiconductor...
Page 431 Register indirect with index addressing. A form of addressing that specifies that the contents of two GPRs be added together to yield the target address for the load or store. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor Glossary-7...
Page 432 Simplified mnemonics. Assembler mnemonics that represent a more complex form of a common operation. Snooping. Monitoring addresses driven by a bus master to detect the need for coherency actions. e200z3 Power Architecture Core Reference Manual, Rev. 2 Glossary-8 Freescale Semiconductor...
Page 433 There are two types of synchronous interrupts, precise and imprecise. System memory. The physical memory available to a processor. TLB (translation lookaside buffer). A cache that holds recently-used page table entries. e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor Glossary-9...
Page 434 Write-through. A cache memory update policy in which all processor write cycles are written to both the cache and memory. e200z3 Power Architecture Core Reference Manual, Rev. 2 Glossary-10 Freescale Semiconductor...
Page 435 (L1CFG0), 2-51 MMU implications, 5-15 debug (hardware) Nexus3 module, see Nexus3 module and cache operation, 9-32 OnCE controller, 9-9–9-31 Carry bit (for integer operations), 2-10 protocol and commands, 9-16 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor Index-1...
Page 436 4-17 rfmci instruction, 1-6 TLB miss exceptions, 5-8 single-precision floating-point (SPFP) instructions, 1-6 block diagram, 1-2 comparisons with legacy PowerPC devices, 1-13 Fixed-interval timer e200z3 Power Architecture Core Reference Manual, Rev. 2 Index-2 Freescale Semiconductor...
Page 437 0 (DSRR0), 2-25 rfdi, 4-32 debug save/restore register 1 (DSRR1), 2-25 rfi, 4-32 machine check syndrome (MCSR), 2-25 scalar floating-point, 1-6 interrupt vector offset (IVORn), 2-21 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor Index-3...
Page 438 (I bit), 2-57 address space, 5-4 endianness (little-endian) bit (E bit), 2-57 address translation guarded memory bit (G bit), 2-57, 5-9 address space, 5-4 memory coherency required bit (M bit), 2-57 e200z3 Power Architecture Core Reference Manual, Rev. 2 Index-4 Freescale Semiconductor...
Page 439 OCR (OnCE control register), 9-20 using tranditional program trace messages, 10-25 OnCE controller interface data trace messaging (DTM) signals, 9-13 message formats, 10-34–10-37 external, 9-14 data read messages, 10-35 internal, 9-14 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor Index-5...
Page 440 1 (SRR1), 2-19, 4-1 condition register (CR), 2-11–2-14 machine state register (MSR), 4-5 CR setting for compare instructions, 2-13 MMU, 2-52–2-59 CR setting for integer instructions, 2-12 e200z3 Power Architecture Core Reference Manual, Rev. 2 Index-6 Freescale Semiconductor...
Page 441 RWCS (read/write access control/status register), 10-14 TCR (timer control register), 2-28 RWD (read/write access data register), 10-16 Terminology conventions, 1-xxx Time base, 2-27 registers Scan chain, 9-24 TBL and TBU, 2-30 e200z3 Power Architecture Core Reference Manual, Rev. 2 Freescale Semiconductor Index-7...
Page 442 Watchpoint signaling, see Debug facilities WBBR (write-back bus register), 9-28 WIMGE bits see Memory/cache access attributes (WIMGE bits), 5-9 WT (watchpoint trigger register), 10-18 XER (integer exception register), 2-10 e200z3 Power Architecture Core Reference Manual, Rev. 2 Index-8 Freescale Semiconductor...

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