Freescale Semiconductor e200z3 Reference Manual page 191

The classifications in Table 4-1
Table 4-2 lists interrupts implemented in the e200z3 and the exception conditions that cause them. Note
that although this table lists system reset, Book E does not define system reset as an interrupt and assigns
no interrupt vector to it.
Interrupt Type IVOR n
1
System reset (not an None
interrupt)
2
Critical input 0
Machine check 1
Data storage 2
Instruction storage 3
2
External input 4
Alignment 5
Program 6
Floating-point 7
unavailable
System call 8
APU unavailable 9
Decrementer 10
Fixed-interval timer 11
Watchdog timer 12
Data TLB error 13
Freescale Semiconductor
are discussed in greater detail in
Table 4-2. Exceptions and Conditions
• Reset by assertion of p_reset_b
• Watchdog timer reset control
• Debug reset control
p_critint_b is asserted and MSR[CE]=1
• p_mcp_b is asserted and MSR[ME] =1
• ISI, ITLB error on first instruction fetch for an exception handler and current
MSR[ME] = 1
• Write bus error on buffered store or cache line push and current MSR[ME]=1
• Bus error (XTE) with MSR[EE]=0 and current MSR[ME]=1
• Non-maskable interrupt ( p_nmi_b recognized asserted) regardless of
MSR[ME]
• Access control
• Byte ordering due to misaligned access across page boundary to pages with
mismatched E bits
• Precise external termination error ( p_d_tea_b assertion and precise
recognition) and MSR[EE]=1
• Access control
• Precise external termination error ( p_i_tea_b assertion and precise
recognition) and MSR[EE]=1
• Byte ordering due to misaligned instruction across page boundary to pages
with mismatched VLE bits, or access to page with VLE set, and E indicating
little-endian.
• Misaligned Instruction fetch due to a change of flow to an odd halfword
instruction boundary on a Book E (non-VLE) instruction page, due to value in
LR, CTR, or xSRR0
p_extint_b is asserted and MSR[EE]=1
• lmw, stmw not word aligned
• lwarx or stwcx. not word aligned
• dcbz with disabled cache, or no cache present, or to W or I storage
Illegal, privileged, trap, floating-point enabled, APU enabled, unimplemented
operation
MSR[FP] = 0 and attempt to execute a Book E floating-point operation
Execution of the system call (sc) instruction
Unused by the e200z3
As specified in Book E
As specified in Book E
As specified in Book E
Data translation lookup did not match a valid TLB entry.
e200z3 Power Architecture Core Reference Manual, Rev. 2
Section 4.6, "Interrupt Definitions."
Cause
Interrupts and Exceptions
Section/Page
—
4.6.1/4-10
4.6.2/4-11
4.6.3/4-13
4.6.4/4-14
4.6.5/4-15
4.6.6/4-16
4.6.7/4-16
4.6.8/4-17
4.6.9/4-18
4.6.10/4-18
4.6.11/4-19
4.6.12/4-19
4.6.13/4-20
4.6.14/4-21
4-3