Freescale Semiconductor e200z3 Reference Manual page 15

Figure
Number
1-1 e200z3 Block Diagram.......................................................................................................... 1-34
1-2 e200z335 Block Diagram...................................................................................................... 1-35
1-3 e200z3 Programmer's Model................................................................................................ 1-39
2-1 e200z3 Programmer's Model.................................................................................................. 2-2
2-2 Machine State Register (MSR) ............................................................................................... 2-6
2-3 Processor ID Register (PIR).................................................................................................... 2-8
2-4 Processor Version Register (PVR) .......................................................................................... 2-9
2-5 System Version Register (SVR).............................................................................................. 2-9
2-6 Integer Exception Register (XER) ........................................................................................ 2-10
2-7 Condition Register (CR) ....................................................................................................... 2-11
2-8 Count Register (CTR) ........................................................................................................... 2-14
2-9 Link Register (LR) ................................................................................................................ 2-15
2-10 Signal Processing and Embedded Floating-Point Status and Control
Register (SPEFSCR) ........................................................................................................ 2-15
2-11 Save/Restore Register 0 (SRR0) ........................................................................................... 2-19
2-12 Save/Restore Register 1 (SRR1) ........................................................................................... 2-19
2-13 Critical Save/Restore Register 0 (CSRR0) ........................................................................... 2-20
2-14 Critical Save/Restore Register 1 (CSRR1) ........................................................................... 2-20
2-15 Data Exception Address Register (DEAR) ........................................................................... 2-20
2-16 Interrupt Vector Prefix Register (IVPR) ............................................................................... 2-21
2-17 Interrupt Vector Offset Registers (IVOR) ............................................................................. 2-21
2-18 Exception Syndrome Register (ESR).................................................................................... 2-23
2-19 Debug Save/Restore Register 0 (DSRR0) ............................................................................ 2-25
2-20 Debug Save/Restore Register 1 (DSRR1) ............................................................................ 2-25
2-21 Machine Check Syndrome Register (MCSR) ....................................................................... 2-26
2-22 Software-Use SPRs (SPRG0-SPRG7 and USPRG0)........................................................... 2-27
2-23 Relationship of Timer Facilities to the Time Base................................................................ 2-27
2-24 Timer Control Register (TCR) .............................................................................................. 2-28
2-25 Timer Status Register (TSR) ................................................................................................. 2-30
2-26 Time Base Upper/Lower Registers (TBU/TBL)................................................................... 2-31
2-27 Decrementer Register (DEC) ................................................................................................ 2-32
2-28 Decrementer Auto-Reload Register (DECAR)..................................................................... 2-32
2-29 Instruction Address Compare Registers (IAC1-IAC4) ........................................................ 2-33
2-30 Data Address Compare Registers (DAC1-DAC2) ............................................................... 2-34
2-31 Data Value Compare Registers (DVC1-DVC2) ................................................................... 2-34
2-32 DBCNT Register................................................................................................................... 2-35
2-33 DBCR0 Register ................................................................................................................... 2-36
2-34 Debug Control Register 1 (DBCR1) ..................................................................................... 2-38
Freescale Semiconductor
Figures
Title
e200z3 Power Architecture Core Reference Manual, Rev. 2
Page
Number
1