Freescale Semiconductor e200z3 Reference Manual page 260

Instruction Pipeline and Execution Timing
point in the FPU pipeline an exception can be guaranteed to not occur. Invalid input operands are detected
in the first stage of the pipeline, while underflow, overflow, and inexactness are determined later in the
pipeline. Best overall performance occurs when either floating-point exceptions are disabled, or when load
and store class instructions are scheduled such that previous floating-point instructions have already
resolved the possibility of exceptional results.
6.7.1.1 SPE Integer Simple Instructions Timing
Instruction timing for SPE integer simple instructions is shown in
These instructions are issued as a pair of operations.
6-22
Table 6-4. Timing for Integer Simple Instructions
Instruction Latency Throughput
brinc 1
evabs 1
evaddiw 1
evaddw 1
evand 1
evandc 1
evcmpeq 1
evcmpgts 1
evcmpgtu 1
evcmplts 1
evcmpltu 1
evcntlsw 1
evcntlzw 1
eveqv 1
evextsb 1
evextsh 1
evmergehi 1
evmergehilo 1
evmergelo 1
evmergelohi 1
evnand 1
evneg 1
evnor 1
evor 1
evorc 1
evrlw 1
e200z3 Power Architecture Core Reference Manual, Rev. 2
Table 6-4. The table is sorted by opcode.
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