Freescale Semiconductor e200z3 Reference Manual page 344

Debug Support
instruction functionality, although JTAG public instructions may be decoded and signaled to external
logic.
The OnCE logic provides for Nexus class 1 static debug capability (using the same set of resources
available to software while the core is in internal debug mode), and is present in all e200z3-based designs.
The OnCE module also provides support for directly integrating a Nexus class 2 or class 3 real-time debug
unit with the core for development of real-time systems where traditional static debug is insufficient. The
partitioning between a OnCE module and a connected Nexus module to provide real-time debugging
allows for capability and cost tradeoffs to be made.
The core is designed to be a fully integratable module. The OnCE TAP controller and associated enabling
logic are designed to allow concatenation with an existing JTAG controller if one is present in the system.
Thus, the core module can be easily integrated with existing JTAG designs or as a stand-alone controller.
To enable full OnCE operation, the jd_enable_once input signal must be asserted. In some system
integrations, this is automatic since the input will be tied asserted. Other integrations may require the
execution of the Enable OnCE command through the TAP and appropriate entry of serial data. Refer to the
documentation for the integrating device. The jd_enable_once input should not change state during a
debug session, or undefined activity may occur.
Figure 9-2 shows the TAP controller and TAP registers implemented by the OnCE logic.
j_tdi
j_tclk
j_tms
j_trst_b
9-12
Auxiliary Data Registers
OnCE Mapped Debug Registers
External Data Registers
Bypass Register
TAP Instruction Register
(OnCE OCMD)
TAP
Controller
Figure 9-2. OnCE TAP Controller and Registers
e200z3 Power Architecture Core Reference Manual, Rev. 2
TDO
Mux Logic
j_tdo
j_tdo_en
Freescale Semiconductor