Freescale Semiconductor e200z3 Reference Manual page 441

Index
MMU assist (MAS0–MAS4, MAS6), 2-54–2-59, 5-14
MMU configuration register (MMUCFG), 2-52
MMU control and status (MMUCSR0), 2-52
process ID register 0 (PID0), 2-59
TLB configuration registers 0–1 (TLBnCFG), 2-53, 5-14
Nexus3
client select control (CSC), 10-10
data trace control (DTC), 10-19
data trace end address 1, 2 (DTEA1, DTEA2), 10-20
data trace start address 1, 2 (DTSA1, DTSA2), 10-20
development control (DC1, DC2), 10-12
development status (DS), 10-14
port configuration (PCR), 10-10
read/write access address (RWA), 10-17
read/write access control/status (RWCS), 10-14
read/write access data (RWD), 10-16
watchpoint trigger (WT), 10-18
processor control
machine state register (MSR), 2-6
processor ID register (PIR), 2-8
processor version register (PVR), 2-8
system version register (SVR), 2-9
reset settings, 2-64
signal processing engine (SPE) APU
accumulator, 2-18
SPEFSCR, 2-15
special-purpose (SPRs)
invalid SPR references, 2-60
software-use SPRs, USPRG0, 2-26
SPRG0-SPRG7, 2-26
summary, 2-61
synchronization requirements for SPRs, 2-60
unimplemented and read-only SPRs, 3-15
time base
TBL and TBU, 2-30
timer control register (TCR), 2-28
timer status register (TSR), 2-29
Reset
common vector, 1-15
register settings, 2-64
reset exception, 4-24
Returning from interrupt handler, 4-32
see also Interrupt handling
rfci, 4-32
rfdi, 3-6, 4-32
rfi, 4-32
RWA (read/write access address register), 10-17
RWCS (read/write access control/status register), 10-14
RWD (read/write access data register), 10-16
S
Scan chain, 9-24
Freescale Semiconductor
e200z3 Power Architecture Core Reference Manual, Rev. 2
Signal processing engine (SPE) APU
registers
accumulator, 2-18
SPEFSCR, 2-15
Signals
core signal definitions, 7-4
debug
OnCE controller signals, 9-13
external, 9-14
internal, 9-14
Nexus3 interface, 10-46
protocol, 10-48
Sleep mode, see Power management
SPE APU unavailable interrupt, 4-25
see also Interrupt handling
SPE floating-point data interrupt, 4-26
see also Interrupt handling
SPE floating-point round interrupt, 4-26
see also Interrupt handling
SPEFSCR (SPE floating-point status and control register),
2-15
SPFP (embedded single-precision floating-point) APUs
floating-point instructions, 3-14–3-15
SPR model
invalid SPR references, 2-60
SPR summary, 2-61
synchronization requirements for SPRs, 2-60
unimplemented and read-only SPRs, 3-15
SPRG0–SPRG7 (software use SPRs), 2-26
SRR0 (save/restore register 0), 2-19, 4-1
SRR1 (save/restore register 1), 2-19, 4-1
stwcx., 3-5, 4-32
Suggested reading list, 1-xxviii
Summary overflow (SO), 2-10
SVR (system version register), 2-9
Synchronization
execution of rfi, 4-32
memory synchronization, 3-4
memory synchronization instructions, 3-4
Synchronization requirements for SPRs, 2-60
System call interrupt, 4-17
see also Interrupt handling
System reset interrupt, 4-24
see also Interrupt handling
T
TBL and TBU (time base registers), 2-30
TCR (timer control register), 2-28
Terminology conventions, 1-xxx
Time base, 2-27
registers
TBL and TBU, 2-30
S–T
Index-7